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hitachi 16-bit single-chip microcomputer h8s/2678 series h8s/2677 hd64f2677, hd6432677 h8s/2676 hd64f2676, hd6432676 h8s/2675 hd6432675 h8s/2673 hd6432673 h8s/2670 hd6412670 reference manual ade-602-192a rev. 2.0 12/5/00 hitachi, ltd.
h8s/2678 series, h8s/2677 f-ztat, h8s/2676 f-ztat reference manual publication date: 1st edition, march 2000 2nd edition, december 2000 published by: electronic devices sales & marketing group semiconductor & integrated circuits hitachi, ltd. edited by: technical documentation group hitachi kodaira semiconductor co., ltd. copyright ?hitachi, ltd., 2000. all rights reserved. printed in japan.
cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products.
main revisions and additions in this edition page item revisions (see manual for details) 6 1.2 block diagram figure 1.1 internal block diagram pllvcc and pllvss pins added 151 4.5.12 burst operation figure 4.29 operation timing in fast page mode (1) title in parentheses amended cast = 1 cast = 0 286 5.16.3 pin functions table 5.35 port g pin functions pg3 to pg0: description amended 291 5.17.3 pin functions table 5.37 port h pin functions ph1 and ph0: description amended 295, 296 5.18.1 port states in each processing state table 5.38 i/o port states in each processing state pg5 and pg4 states amended 378 to 380 7.1.2 dc characteristics table 7.2 dc characteristics entire table amended table 7.3 permissible output currents max. values of i ol and ? oh amended 384 7.1.3 ac characteristics figure 7.3 (2) oscillation stabilization timing added 414 figure 7.36 wdt output timing amended 417 7.2.1 absolute maximum ratings table 7.11 absolute maximum ratings note: operating temperature ranges amended 418, 419 7.2.2 dc characteristics table 7.12 dc characteristics entire table amended 420 table 7.13 permissible output currents max. values of i ol and ? oh amended 432, 433 7.2.6 flash memory characteristics conditions: operating temperature range amended unit of t e amended z and amended

organization of h8s/2678 series reference manual the following manuals are available for h8s/2678 series products. table 1 h8s/2678 series manuals title document code h8s/2600 series, h8s/2000 series programming manual ade-602-083a h8s/2678 series hardware manual ade-602-193a h8s/2678 series reference manual ade-602-192a the h8s/2600 series, h8s/2000 series programming manual gives a detailed description of the architecture and instruction set of the h8s/2600 cpu incorporated into h8s/2678 series products. the h8s/2678 series hardware manual describes the operation of on-chip functions common to h8s/2678 series products, and gives a detailed description of the related registers. the h8s/2678 series reference manual mainly covers information specific to h8s/2678 series products, including pin arrangement, i/o ports, mcu operating modes (memory maps), interrupt vectors, bus control, and electrical characteristics, and also includes a brief description of all i/o registers for the convenience of the user.
the contents of the h8s/2678 series hardware manual and the h8s/2678 series reference manual are summarized in table 2. table 2 contents of hardware manual and reference manual no. item hardware manual reference manual 1 overview (including pin arrangement) 2 mcu operating modes (including memory maps) 3 exception handling 4 interrupt controller 5 bus controller 6 dma controller (dmac) 7 data transfer controller (dtc) 8 16-bit timer unit (tpu) 9 programmable pulse generator (ppg) 10 8-bit timers 11 watchdog timer 12 serial communication interface (sci) 13 smart card interface 14 a/d converter 15 d/a converter 16 ram 17 rom (flash memory) 18 clock pulse generator 19 power-down modes 20 i/o ports (including port block diagrams) 21 electrical characteristics 22 register reference chart (in address order, with function summary) 23 instruction set 24 package dimension diagrams : included : included (with detailed register descriptions) ? not included
the following chart shows where to find various kinds of information for different purposes. overview pin arrangement diagram block diagrams of function modules pin functions electrical characteristics for product evaluation information, or comparative specification information for current users of hitachi products 1.1 overview 1.3 pin arrangement section 6 peripheral block diagrams 1.5 pin functions section 7 electrical characteristics i/o port information interrupts and exception handling information on other modules pin functions for detailed information on functions section 5 i/o ports section 3 exception handling and interrupt controller h8s/2678 series hardware manual 1.5 pin functions list detailed descriptions 1.4 pin functions in each operating mode section 2 mcu operating modes list to find a register from its address to find register information by function setting procedure and notes for use as design material section 8 registers 8.1 list of registers (address order) 8.2 list of registers (by module) h8s/2678 series hardware manual list operation description and notes program examples h8s/2600 series, h8s/2000 series programming manual for h8s/2678 series specifications for details of operation of h8s/2678 series modules for information on h8s/2678 series operating modes for information on h8s/2678 series registers for information on h8s/2678 series instructions

i contents section 1 overview ........................................................................................................... 1 1.1 overview................................................................................................................... ......... 1 1.2 block diagram.............................................................................................................. ..... 6 1.3 pin arrangement ............................................................................................................ .... 7 1.4 pin functions in each operating mode............................................................................. 8 1.5 pin functions .............................................................................................................. ....... 20 1.6 product lineup............................................................................................................. ...... 28 1.7 package dimensions ......................................................................................................... .28 section 2 mcu operating modes ................................................................................. 29 2.1 overview................................................................................................................... ......... 29 2.1.1 operating mode selection (f-ztat version)..................................................... 29 2.1.2 operating mode selection (romless and mask rom versions) ....................... 31 2.1.3 register configuration ......................................................................................... 33 2.2 register descriptions....................................................................................................... .. 3 3 2.2.1 mode control register (mdcr) .......................................................................... 33 2.2.2 system control register (syscr)....................................................................... 34 2.3 operating mode descriptions ............................................................................................ 35 2.3.1 mode 1 (expanded mode with on-chip rom disabled) ................................... 35 2.3.2 mode 2 (expanded mode with on-chip rom disabled) ................................... 35 2.3.3 mode 3 .................................................................................................................. 3 5 2.3.4 mode 4 (expanded mode with on-chip rom enabled)..................................... 36 2.3.5 mode 5 (external rom activation expanded mode with on-chip rom enabled)................................................................................................................ 36 2.3.6 mode 6 (external rom activation expanded mode with on-chip rom enabled)................................................................................................................ 36 2.3.7 mode 7 (single-chip activation mode with on-chip rom enabled) ............... 36 2.3.8 modes 8 and 9 [f-ztat version only]............................................................... 37 2.3.9 mode 10 [f-ztat version only]........................................................................ 37 2.3.10 mode 11 ................................................................................................................ 3 7 2.3.11 mode 12 ............................................................................................................... 3 7 2.3.12 modes 13 and 14 [f-ztat version only]........................................................... 37 2.3.13 mode 15 [f-ztat version only]........................................................................ 37 2.4 pin functions in each operating mode............................................................................. 38 2.5 memory map in each operating mode............................................................................. 39 section 3 exception handling and interrupt controller ......................................... 53 3.1 overview................................................................................................................... ......... 53 3.1.1 exception handling types and priority ............................................................... 53
ii 3.2 interrupt controller ....................................................................................................... ..... 54 3.2.1 interrupt controller features ................................................................................ 54 3.2.2 block diagram...................................................................................................... 55 3.2.3 pin configuration ................................................................................................. 56 3.2.4 register configuration ......................................................................................... 57 3.3 register descriptions...................................................................................................... ... 58 3.3.1 interrupt control register (intcr)..................................................................... 58 3.3.2 interrupt priority registers a to k (ipra to iprk) ............................................ 59 3.3.3 irq enable register (ier)................................................................................... 60 3.3.4 irq sense control registers h and l (iscrh, iscrl)..................................... 61 3.3.5 irq status register (isr) .................................................................................... 62 3.3.6 irq pin select register (itsr) ........................................................................... 64 3.3.7 software standby release irq enable register (ssier) ................................... 65 3.4 interrupt sources.......................................................................................................... ...... 66 3.4.1 external interrupts ................................................................................................ 66 3.4.2 internal interrupts ................................................................................................. 67 3.4.3 interrupt vector table .......................................................................................... 68 3.5 interrupt operation........................................................................................................ ..... 74 3.5.1 interrupt control modes and interrupt operation ................................................ 74 3.5.2 interrupt control mode 0...................................................................................... 77 3.5.3 interrupt control mode 2...................................................................................... 79 3.5.4 interrupt exception handling sequence............................................................... 81 3.5.5 interrupt response times..................................................................................... 83 3.6 usage notes ................................................................................................................ ....... 84 3.6.1 contention between interrupt generation and disabling..................................... 84 3.6.2 instructions that disable interrupts....................................................................... 85 3.6.3 periods when interrupts are disabled................................................................... 85 3.6.4 interrupts during execution of eepmov instruction .......................................... 85 3.7 dtc and dmac activation by interrupt.......................................................................... 85 3.7.1 overview............................................................................................................... 85 3.7.2 block diagram...................................................................................................... 86 3.7.3 operation .............................................................................................................. 87 section 4 bus controller .................................................................................................. 91 4.1 overview................................................................................................................... ......... 91 4.1.1 features................................................................................................................. 91 4.1.2 block diagram ..................................................................................................... 93 4.1.3 pin configuration ................................................................................................. 94 4.1.4 register configuration ......................................................................................... 96 4.2 register descriptions...................................................................................................... ... 97 4.2.1 bus width control register (abwcr) ............................................................... 97 4.2.2 access state control register (astcr).............................................................. 97 4.2.3 wait control registers a and b (wtcra, wtcrb)......................................... 98
iii 4.2.4 read strobe timing control register (rdncr)................................................. 99 4.2.5 cs assertion period control registers (csacrh, csacrl) ........................... 101 4.2.6 area 0 burst rom i/f control register (bromcrh) area 1 burst rom i/f control register (bromcrl) ....................................... 103 4.2.7 bus control register (bcr)................................................................................. 105 4.2.8 dram control register (dramcr).................................................................. 107 4.2.9 dram access control register (draccr) ...................................................... 112 4.2.10 refresh control register (refcr) ...................................................................... 113 4.2.11 refresh timer counter (rtcnt) ........................................................................ 117 4.2.12 refresh time control register (rtcor)............................................................ 117 4.3 overview of bus control................................................................................................... 1 18 4.3.1 area division........................................................................................................ 118 4.3.2 bus specifications ................................................................................................ 119 4.3.3 memory interfaces................................................................................................ 120 4.3.4 chip select signals............................................................................................... 122 4.4 basic bus interface ........................................................................................................ .... 123 4.4.1 overview............................................................................................................... 12 3 4.4.2 data size and data alignment ............................................................................. 123 4.4.3 valid strobes ........................................................................................................ 124 4.4.4 basic timing......................................................................................................... 126 4.4.5 wait control ......................................................................................................... 134 4.4.6 read strobe ( rd ) timing..................................................................................... 136 4.4.7 extension of chip select ( cs ) assertion period .................................................. 137 4.5 dram interface ............................................................................................................. ... 138 4.5.1 overview............................................................................................................... 13 8 4.5.2 setting dram space ........................................................................................... 138 4.5.3 address multiplexing ........................................................................................... 139 4.5.4 data bus ............................................................................................................... 13 9 4.5.5 pins used for dram interface ............................................................................ 140 4.5.6 basic timing......................................................................................................... 141 4.5.7 column address output cycle control ............................................................... 142 4.5.8 row address output cycle control..................................................................... 143 4.5.9 precharge state control ........................................................................................ 145 4.5.10 wait control ......................................................................................................... 146 4.5.11 byte access control ............................................................................................. 149 4.5.12 burst operation..................................................................................................... 150 4.5.13 refresh control..................................................................................................... 154 4.5.14 dmac and exdmac single address transfer mode and dram interface .... 159 4.6 burst rom interface ........................................................................................................ . 162 4.6.1 overview............................................................................................................... 16 2 4.6.2 basic timing......................................................................................................... 162 4.6.3 wait control ......................................................................................................... 164 4.6.4 write access......................................................................................................... 164
iv 4.7 idle cycle................................................................................................................. .......... 165 4.7.1 operation .............................................................................................................. 16 5 4.7.2 pin states in idle cycle......................................................................................... 173 4.8 write data buffer function ............................................................................................... 17 3 4.9 bus release................................................................................................................ ........ 174 4.9.1 overview............................................................................................................... 17 4 4.9.2 operation .............................................................................................................. 17 5 4.9.3 pin states in external bus released state ............................................................ 176 4.9.4 transition timing................................................................................................. 177 4.9.5 usage notes .......................................................................................................... 178 4.10 bus arbitration........................................................................................................... ........ 179 4.10.1 overview............................................................................................................... 1 79 4.10.2 operation .............................................................................................................. 1 79 4.10.3 bus transfer timing............................................................................................. 180 4.11 bus controller operation in a reset .................................................................................. 181 section 5 i/o ports ............................................................................................................. 183 5.1 overview................................................................................................................... ......... 183 5.2 port 1..................................................................................................................... ............. 192 5.2.1 overview............................................................................................................... 19 2 5.2.2 register configuration ......................................................................................... 193 5.2.3 pin functions ........................................................................................................ 194 5.3 port 2..................................................................................................................... ............. 203 5.3.1 overview............................................................................................................... 20 3 5.3.2 register configuration ......................................................................................... 204 5.3.3 pin functions ........................................................................................................ 205 5.4 port 3..................................................................................................................... ............. 214 5.4.1 overview............................................................................................................... 21 4 5.4.2 register configuration ......................................................................................... 215 5.4.3 pin functions ........................................................................................................ 217 5.5 port 4..................................................................................................................... ............. 220 5.5.1 overview............................................................................................................... 22 0 5.5.2 register configuration ......................................................................................... 220 5.5.3 pin functions ........................................................................................................ 221 5.6 port 5..................................................................................................................... ............. 222 5.6.1 overview............................................................................................................... 22 2 5.6.2 register configuration ......................................................................................... 222 5.6.3 pin functions ........................................................................................................ 224 5.7 port 6..................................................................................................................... ............. 227 5.7.1 overview............................................................................................................... 22 7 5.7.2 register configuration ......................................................................................... 227 5.7.3 pin functions ........................................................................................................ 229 5.8 port 7..................................................................................................................... ............. 233
v 5.8.1 overview............................................................................................................... 23 3 5.8.2 register configuration ......................................................................................... 234 5.8.3 pin functions ........................................................................................................ 236 5.9 port 8..................................................................................................................... ............. 240 5.9.1 overview............................................................................................................... 24 0 5.9.2 register configuration ......................................................................................... 241 5.9.3 pin functions ........................................................................................................ 242 5.10 port a.................................................................................................................... ............. 246 5.10.1 overview............................................................................................................... 2 46 5.10.2 register configuration ......................................................................................... 247 5.10.3 pin functions ........................................................................................................ 252 5.10.4 mos input pull-up function ............................................................................... 253 5.11 port b .................................................................................................................... ............. 254 5.11.1 overview............................................................................................................... 2 54 5.11.2 register configuration ......................................................................................... 255 5.11.3 pin functions ........................................................................................................ 257 5.11.4 mos input pull-up function ............................................................................... 258 5.12 port c .................................................................................................................... ............. 259 5.12.1 overview............................................................................................................... 2 59 5.12.2 register configuration ......................................................................................... 260 5.12.3 pin functions ........................................................................................................ 262 5.12.4 mos input pull-up function ............................................................................... 263 5.13 port d.................................................................................................................... ............. 264 5.13.1 overview............................................................................................................... 2 64 5.13.2 register configuration ......................................................................................... 265 5.13.3 pin functions ........................................................................................................ 267 5.13.4 mos input pull-up function ............................................................................... 268 5.14 port e .................................................................................................................... ............. 269 5.14.1 overview............................................................................................................... 2 69 5.14.2 register configuration ......................................................................................... 270 5.14.3 pin functions ........................................................................................................ 272 5.14.4 mos input pull-up function ............................................................................... 273 5.15 port f .................................................................................................................... ............. 274 5.15.1 overview............................................................................................................... 2 74 5.15.2 register configuration ......................................................................................... 275 5.15.3 pin functions ........................................................................................................ 278 5.16 port g.................................................................................................................... ............. 282 5.16.1 overview............................................................................................................... 2 82 5.16.2 register configuration ......................................................................................... 282 5.16.3 pin functions ........................................................................................................ 285 5.17 port h.................................................................................................................... ............. 287 5.17.1 overview............................................................................................................... 2 87 5.17.2 register configuration ......................................................................................... 287
vi 5.17.3 pin functions ........................................................................................................ 290 5.18 pin functions ............................................................................................................. ........ 292 5.18.1 port states in each processing state..................................................................... 292 5.19 i/o port block diagrams ................................................................................................... 297 5.19.1 port 1.................................................................................................................. ... 297 5.19.2 port 2.................................................................................................................. ... 301 5.19.3 port 3.................................................................................................................. ... 303 5.19.4 port 4.................................................................................................................. ... 307 5.19.5 port 5.................................................................................................................. ... 308 5.19.6 port 6.................................................................................................................. ... 313 5.19.7 port 7.................................................................................................................. ... 316 5.19.8 port 8.................................................................................................................. ... 319 5.19.9 port a.................................................................................................................. .. 322 5.19.10 port b ................................................................................................................. ... 324 5.19.11 port c ................................................................................................................. ... 325 5.19.12 port d................................................................................................................. ... 326 5.19.13 port e ................................................................................................................. ... 327 5.19.14 port f ................................................................................................................. ... 328 5.19.15 port g................................................................................................................. ... 336 5.19.16 port h................................................................................................................. ... 341 section 6 supporting module block diagrams ........................................................ 345 6.1 interrupt controller ....................................................................................................... ..... 345 6.1.1 features................................................................................................................. 345 6.1.2 block diagram...................................................................................................... 345 6.1.3 pins ..................................................................................................................... .. 346 6.2 dma controller............................................................................................................. .... 346 6.2.1 features................................................................................................................. 346 6.2.2 block diagram...................................................................................................... 347 6.2.3 pins ..................................................................................................................... .. 348 6.3 data transfer controller ................................................................................................... . 348 6.3.1 features................................................................................................................. 348 6.3.2 block diagram...................................................................................................... 349 6.4 exdma controller (exdmac) ...................................................................................... 350 6.4.1 features................................................................................................................. 350 6.4.2 block diagram...................................................................................................... 351 6.4.3 pins ..................................................................................................................... .. 352 6.5 16-bit timer pulse unit .................................................................................................... . 353 6.5.1 features................................................................................................................. 353 6.5.2 block diagram...................................................................................................... 354 6.5.3 pins ..................................................................................................................... .. 355 6.6 programmable pulse generator ......................................................................................... 356 6.6.1 features................................................................................................................. 356
vii 6.6.2 block diagram...................................................................................................... 357 6.6.3 pins ..................................................................................................................... .. 358 6.7 8-bit timer................................................................................................................ ......... 358 6.7.1 features................................................................................................................. 358 6.7.2 block diagram...................................................................................................... 359 6.7.3 pins ..................................................................................................................... .. 360 6.8 watchdog timer ............................................................................................................. ... 360 6.8.1 features................................................................................................................. 360 6.8.2 block diagram...................................................................................................... 361 6.8.3 pins ..................................................................................................................... .. 361 6.9 serial communication interface ........................................................................................ 362 6.9.1 features................................................................................................................. 362 6.9.2 block diagram...................................................................................................... 362 6.9.3 pins ..................................................................................................................... .. 363 6.10 smart card interface ...................................................................................................... .... 364 6.10.1 features................................................................................................................ . 364 6.10.2 block diagram...................................................................................................... 364 6.10.3 pins .................................................................................................................... ... 365 6.11 irda...................................................................................................................... ............. 365 6.11.1 features................................................................................................................ . 365 6.11.2 block diagram...................................................................................................... 366 6.11.3 pins .................................................................................................................... ... 366 6.12 a/d converter ............................................................................................................. ...... 367 6.12.1 features................................................................................................................ . 367 6.12.2 block diagram...................................................................................................... 368 6.12.3 pins .................................................................................................................... ... 369 6.13 d/a converter ............................................................................................................. ...... 370 6.13.1 features................................................................................................................ . 370 6.13.2 block diagram...................................................................................................... 370 6.13.3 pins .................................................................................................................... ... 371 6.14 ram ....................................................................................................................... ........... 372 6.14.1 features................................................................................................................ . 372 6.14.2 block diagram...................................................................................................... 372 6.15 rom ....................................................................................................................... ........... 373 6.15.1 features................................................................................................................ . 373 6.15.2 block diagrams .................................................................................................... 373 6.16 clock pulse generator ..................................................................................................... .. 375 6.16.1 features................................................................................................................ . 375 6.16.2 block diagram...................................................................................................... 375 section 7 electrical characteristics .............................................................................. 377 7.1 electrical characteristics of mask rom version (h8s/2677, h8s/2676, h8s/2675, h8s/2673) and romless version (h8s/2670) ................................................................. 377
viii 7.1.1 absolute maximum ratings................................................................................. 377 7.1.2 dc characteristics ................................................................................................ 378 7.1.3 ac characteristics ................................................................................................ 381 7.1.4 conversion characteristics................................................................................... 415 7.1.5 d/a conversion characteristics ........................................................................... 416 7.2 electrical characteristics of f-ztat version (h8s/2677, h8s/2676)............................. 417 7.2.1 absolute maximum ratings................................................................................. 417 7.2.2 dc characteristics ................................................................................................ 418 7.2.3 ac characteristics ................................................................................................ 421 7.2.4 a/d conversion characteristics ........................................................................... 430 7.2.5 d/a conversion characteristics ........................................................................... 431 7.2.6 flash memory characteristics .............................................................................. 432 7.3 usage note................................................................................................................. ........ 434 section 8 registers ............................................................................................................ 435 8.1 list of registers (address order) ...................................................................................... 435 8.2 list of registers (by module) ........................................................................................... 447 8.3 register descriptions...................................................................................................... ... 458
1 section 1 overview 1.1 overview the h8s/2678 series comprises microcomputers (mcus), built around the h8s/2600 cpu, employing hitachi? original architecture, and equipped with on-chip supporting functions necessary for system configuration. the h8s/2600 cpu has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-mbyte linear address space. the instruction set is upward-compatible with h8/300 and h8/300h cpu instructions at the object-code level, facilitating migration from the h8/300, h8/300l, or h8/300h series. on-chip supporting functions required for system configuration include direct memory access controller (dmac), exdma controller (exdmac), and data transfer controller (dtc) bus masters, rom and ram memory, a16-bit timer pulse unit (tpu), programmable pulse generator (ppg), 8-bit timer module (tmr), watchdog timer module (wdt), serial communication interfaces (sci, irda), a/d converter, d/a converter, and i/o ports. a high-functionality bus controller is also provided, enabling fast and easy connection of dram and other kinds of memory. the on-chip rom is either single-power-supply flash memory (f-ztat*) or mask rom, enabling users to respond quickly and flexibly to changing application specifications, growing production volumes, and other conditions. the rom is connected to the cpu via a 16-bit data bus, enabling both byte and word data to be accessed in one state. instruction fetching is thus speeded up, and processing speed increased. the features of the h8s/2678 series are shown in table 1.1. note: * f-ztat is a trademark of hitachi, ltd.
2 table 1.1 overview item specifications cpu ? general-register architecture ? sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) ? high-speed operation suitable for realtime control ? maximum operating frequency: 33 mhz ? high-speed arithmetic operations 8/16/32-bit register-register add/subtract: 30 ns (33 mhz operation) 16 16-bit register-register multiply: 90 ns (33 mhz operation) 32 ?16-bit register-register divide: 600 ns (33 mhz operation) ? instruction set suitable for high-speed operation ? sixty-five basic instructions ? 8/16/32-bit transfer/arithmetic and logic instructions ? unsigned/signed multiply and divide instructions ? powerful bit-manipulation instructions ? cpu operating mode ? advanced mode: 16-mbyte address space bus controller ? address space divided into 8 areas, with bus specifications settable independently for each area ? chip select output possible for each area ? selection of 8-bit or 16-bit access space for each area ? 2-state or 3-state access space can be designated for each area ? number of program wait states can be set for each area ? maximum 8-mbyte dram directly connectable (or use of interval timer possible) ? external bus release function dma controller (dmac) ? selection of short address mode or full address mode ? four channels in short address mode, two channels in full address mode ? transfer possible in repeat mode, block transfer mode, etc. ? single address mode transfer possible ? can be activated by internal interrupt
3 item specifications exdma controller (exdmac) ? four dma channels exclusively for external bus use ? selection of dual address mode or single address mode ? transfer possible in burst transfer mode, block transfer mode, etc. ? repeat area setting function ? can operate in parallel with internal bus operations by internal bus master data transfer controller (dtc) ? activated by internal interrupt or software ? multiple transfers or multiple types of transfer possible for one activation source ? transfer possible in repeat mode, block transfer mode, etc. ? request can be sent to cpu for interrupt that activated dtc 16-bit timer-pulse unit (tpu) ? six-channel 16-bit timer on-chip ? pulse i/o processing capability for up to 16 pins ? automatic 2-phase encoder count capability programmable pulse generator (ppg) ? maximum 16-bit pulse output possible with tpu as time base ? output trigger selectable in 4-bit groups ? non-overlap margin can be set ? direct output or inverse output setting possible 8-bit timer, 2 channels ? 8-bit up-counter (external event count capability) ? two time constant registers ? two-channel connection possible watchdog timer ? watchdog timer or interval timer selectable serial communi- cation interface (sci), 3 channels ? asynchronous mode or synchronous mode selectable ? multiprocessor communication function ? smart card interface function ? one channel (sci0) functions as sci with irda ? conforms to irda specification ver. 1.0 ? irda format encoding/decoding of txd and rxd
4 item specifications a/d converter ? resolution: 10 bits ? input: 12 channels ? 6.7 ? minimum conversion time (at 20 mhz operation) ? single or scan mode selectable ? sample-and-hold function ? a/d conversion can be activated by external trigger or timer trigger d/a converter ? resolution: 8 bits ? output: 4 channels i/o ports ? 103 input/output pins, 12 input pins memory ? flash memory, mask rom ? high-speed static ram product name rom/ram (bytes) f-ztat version mask rom version romless version h8s/2677 384 k/8 k in planning stage in planning stage h8s/2676 256 k/8 k hd64f2676 hd6432676 h8s/2675 128 k/8 k in planning stage h8s/2673 64 k/8 k hd6432673 h8s/2670 ?8 k hd6412670 interrupt controller ? 17 external interrupt pins (nmi, irq0 to irq15 ) ? 56 internal interrupt sources ? eight interrupt priority levels settable power-down state ? clock division mode ? sleep mode ? module stop mode ? software standby mode ? hardware standby mode
5 item specifications operating modes ? selection of twelve mcu operating modes (f-ztat version) mcu cpu external data bus operating mode operating mode description on-chip rom initial value maximum value 0 1 advanced expanded mode with on-chip rom disabled 16 bits 16 bits 2 disabled 8 bits 16 bits 3 4 expanded mode with on-chip rom enabled enabled 8 bits 16 bits 5 external rom activation expanded enabled 16 bits 16 bits 6 mode with on-chip rom enabled 8 bits 16 bits 7 single-chip activation mode with on-chip rom enabled enabled 16 bits 8 9 10 advanced boot mode enabled 8 bits 16 bits 11 12 advanced user program mode enabled 8 bits 16 bits 13 16 bits 16 bits 14 advanced user program mode enabled 8 bits 16 bits 15 16 bits ? selection of six mcu operating modes (mask rom version, romless version) mcu cpu external data bus operating mode operating mode description on-chip rom initial value maximum value 0 1 * advanced expanded mode with on-chip rom disabled 16 bits 16 bits 2 * disabled 8 bits 16 bits 3 4 advanced expanded mode with on-chip rom enabled enabled 8 bits 16 bits 5 external rom activation expanded enabled 16 bits 16 bits 6 mode with on-chip rom enabled 8 bits 16 bits 7 single-chip activation mode with on-chip rom enabled enabled 16 bits note: * only modes 1 and 2 are available in the romless version. clock pulse generator ? built-in pll circuits ( 1, 2, 4) input clock frequency (2 to 33 mhz) packages ? 144-pin plastic qfp (fp-144)
6 1.2 block diagram pe7/d7 pe6/d6 pe5/d5 pe4/d4 pe3/d3 pe2/d2 pe1/d1 pe0/d0 internal data bus peripheral address bus peripheral data bus pd7/d15 pd6/d14 pd5/d13 pd4/d12 pd3/d11 pd2/d10 pd1/d9 pd0/d8 port d pllvcc pllvss vcc vcc vcc vcc vcc vss vss vss vss vss vss vss pa7 / a23 pa6 / a22 pa5 / a21 pa4 / a20 pa3 / a19 pa2 / a18 pa1 / a17 pa0 / a16 pb7 / a15 pb6 / a14 pb5 / a13 pb4 / a12 pb3 / a11 pb2/a10 pb1/a9 pb0/a8 pc7/a7 pc6/a6 pc5/a5 pc4/a4 pc3/a3 pc2/a2 pc1/a1 pc0/a0 p35 / sck1/( oe irq7 irq6 irq5 irq4 adtrg irq3 irq2 irq1 irq0 irq8 irq9 irq10 irq11 irq12 irq13 edrak0 irq14 edrak1 irq15 edrak2 edrak3 dack1 irq13 dack0 irq12 tend1 irq11 tend0 irq10 dreq1 irq9 dreq0 irq8 breq back breqo cs3 cs2 cs1 cs0 pf6 / as rd hwr lwr lcas irq15 ucas irq14 wait stby res wdtovf edack1 dack1 edack0 dack0 etend1 tend1 etend0 tend0 edreq1 dreq1 edreq0 dreq0 cs7 oe irq7 cs6 irq6 cs5 cs4 edack3 irq5 edack2 irq4 etend3 irq3 etend2 irq2 edreq3 irq1 edreq2 irq0 figure 1.1 internal block diagram
7 1.3 pin arrangement md2 p83 / etend3 irq3 edack2 irq4 edack3 irq5 edreq0 dreq0 edreq1 dreq1 etend0 tend0 irq1 irq0 cs5 cs4 cs3 cs2 cs1 cs0 stby pllvcc res as rd hwr lwr lcas irq15 ucas irq14 wait dack1 irq13 dack0 irq12 tend1 irq11 tend0 irq10 irq2 adtrg irq3 cs6 irq6 cs7 oe irq7 breqo back breq irq4 irq5 irq6 irq7 oe edreq2 irq0 edreq3 irq1 etend2 irq2 dreq1 irq9 dreq0 irq8 edrak1 irq15 edrak0 irq14 irq13 irq12 irq11 irq10 irq9 irq8 edrak3 edrak2 edack1 dack1 edack0 dack0 etend1 tend1 wdtovf figure 1.2 pin arrangement (fp-144: top view)
8 1.4 pin functions in each operating mode table 1.2 pin functions in each operating mode pin name flash memory pin no. mode 1 mode 2 mode 4 mode 5 mode 6 mode 7 program- mer mode 1 md2 md2 md2 md2 md2 md2 vss 2 p83/ etend3 irq3 etend3 irq3 etend3 irq3 etend3 irq3 etend3 irq3 etend3 irq3 irq3 edack2 irq4 edack2 irq4 edack2 irq4 edack2 irq4 edack2 irq4 edack2 irq4 irq4 edack3 irq5 edack3 irq5 edack3 irq5 edack3 irq5 edack3 irq5 edack3 irq5 irq5
9 pin name flash memory pin no. mode 1 mode 2 mode 4 mode 5 mode 6 mode 7 program- mer mode 11 a5 a5 pc5/a5 a5 a5 when expe = 1: pc5/a5 when expe = 0: pc5 a5 12 vss vss vss vss vss vss vss 13 a6 a6 pc6/a6 a6 a6 when expe = 1: pc6/a6 when expe = 0: pc6 a6 14 a7 a7 pc7/a7 a7 a7 when expe = 1: pc7/a7 when expe = 0: pc7 a7 15 a8 a8 pb0/a8 a8 a8 when expe = 1: pb0/a8 when expe = 0: pb0 a8 16 a9 a9 pb1/a9 a9 a9 when expe = 1: pb1/a9 when expe = 0: pb1 a9 17 a10 a10 pb2/a10 a10 a10 when expe = 1: pb2/a10 when expe = 0: pb2 a10 18 a11 a11 pb3/a11 a11 a11 when expe = 1: pb3/a11 when expe = 0: pb3 a11 19 vss vss vss vss vss vss vss 20 a12 a12 pb4/a12 a12 a12 when expe = 1: pb4/a12 when expe = 0: pb4 a12 21 a13 a13 pb5/a13 a13 a13 when expe = 1: pb5/a13 when expe = 0: pb5 a13
10 pin name flash memory pin no. mode 1 mode 2 mode 4 mode 5 mode 6 mode 7 program- mer mode 22 a14 a14 pb6/a14 a14 a14 when expe = 1: pb6/a14 when expe = 0: pb6 a14 23 a15 a15 pb7/a15 a15 a15 when expe = 1: pb7/a15 when expe = 0: pb7 a15 24 a16 a16 pa0/a16 a16 a16 when expe = 1: pa0/a16 when expe = 0: pa0 a16 25 a17 a17 pa1/a17 a17 a17 when expe = 1: pa1/a17 when expe = 0: pa1 a17 26 vss vss vss vss vss vss vss 27 a18 a18 pa2/a18 a18 a18 when expe = 1: pa2/a18 when expe = 0: pa2 a18 28 a19 a19 pa3/a19 a19 a19 when expe = 1: pa3/a19 when expe = 0: pa3 nc 29 a20 a20 pa4/a20 a20 a20 when expe = 1: pa4/a20 when expe = 0: pa4 nc 30 pa5/a21 pa5/a21 pa5/a21 pa5/a21 pa5/a21 when expe = 1: pa5/a21 when expe = 0: pa5 nc 31 pa6/a22 pa6/a22 pa6/a22 pa6/a22 pa6/a22 when expe = 1: pa6/a22 when expe = 0: pa6 nc
11 pin name flash memory pin no. mode 1 mode 2 mode 4 mode 5 mode 6 mode 7 program- mer mode 32 pa7/a23 pa7/a23 pa7/a23 pa7/a23 pa7/a23 when expe = 1: pa7/a23 when expe = 0: pa7 nc 33 nc nc nc nc nc nc nc 34 p70/ edreq0 dreq0 edreq0 dreq0 edreq0 dreq0 edreq0 dreq0 edreq0 dreq0 edreq0 dreq0 dreq0 edreq1 dreq1 edreq1 dreq1 edreq1 dreq1 edreq1 dreq1 edreq1 dreq1 edreq1 dreq1 dreq1 etend0 tend0 etend0 tend0 etend0 tend0 etend0 tend0 etend0 tend0 etend0 tend0 wdtovf wdtovf wdtovf wdtovf wdtovf wdtovf etend1 tend1 etend1 tend1 etend1 tend1 etend1 tend1 etend1 tend1 etend1 tend1 tend1 edack0 dack0 edack0 dack0 edack0 dack0 edack0 dack0 edack0 dack0 edack0 dack0 dack0 edack1 dack1 edack1 dack1 edack1 dack1 edack1 dack1 edack1 dack1 edack1 dack1 dack1
12 pin name flash memory pin no. mode 1 mode 2 mode 4 mode 5 mode 6 mode 7 program- mer mode 44 p11/po9/ tiocb0 p11/po9/ tiocb0 p11/po9/ tiocb0 p11/po9/ tiocb0 p11/po9/ tiocb0 p11/po9/ tiocb0 nc 45 p12/po10/ tiocc0/ tclka p12/po10/ tiocc0/ tclka p12/po10/ tiocc0/ tclka p12/po10/ tiocc0/ tclka p12/po10/ tiocc0/ tclka p12/po10/ tiocc0/ tclka nc 46 p13/po11/ tiocd0/ tclkb p13/po11/ tiocd0/ tclkb p13/po11/ tiocd0/ tclkb p13/po11/ tiocd0/ tclkb p13/po11/ tiocd0/ tclkb p13/po11/ tiocd0/ tclkb nc 47 vss vss vss vss vss vss vss 48 p14/po12/ tioca1 p14/po12/ tioca1 p14/po12/ tioca1 p14/po12/ tioca1 p14/po12/ tioca1 p14/po12/ tioca1 nc 49 p15/po13/ tiocb1/ tclkc p15/po13/ tiocb1/ tclkc p15/po13/ tiocb1/ tclkc p15/po13/ tiocb1/ tclkc p15/po13/ tiocb1/ tclkc p15/po13/ tiocb1/ tclkc nc 50 p16/po14/ tioca2/ edrak2 edrak2 edrak2 edrak2 edrak2 edrak2 edrak3 edrak3 edrak3 edrak3 edrak3 e drak3 irq8 irq8 irq8 irq8 irq8 irq8 irq9 irq9 irq9 irq9 irq9 irq9 irq10 irq10 irq10 irq10 irq10 irq10 oe irq11 irq11 irq11 irq11 irq11 irq11 ce
13 pin name flash memory pin no. mode 1 mode 2 mode 4 mode 5 mode 6 mode 7 program- mer mode 56 p24/po4/ tioca4/ ( irq12 irq12 irq12 irq12 irq12 irq12 we irq13 irq13 irq13 irq13 irq13 irq13 edrak0 irq14 edrak0 irq14 edrak0 irq14 edrak0 irq14 edrak0 irq14 edrak0 irq14 irq14 edrak1 irq15 edrak1 irq15 edrak1 irq15 edrak1 irq15 edrak1 irq15 edrak1 irq15 irq15 dreq0 irq8 dreq0 irq8 dreq0 irq8 dreq0 irq8 dreq0 irq8 dreq0 irq8 dreq1 irq9 dreq1 irq9 dreq1 irq9 dreq1 irq9 dreq1 irq9 dreq1 irq9
14 pin name flash memory pin no. mode 1 mode 2 mode 4 mode 5 mode 6 mode 7 program- mer mode 66 d4 pe4/d4 pe4/d4 d4 pe4/d4 when expe = 1: pe4/d4 when expe = 0: pe4 nc 67 vcc vcc vcc vcc vcc vcc vcc 68 d3 pe3/d3 pe3/d3 d3 pe3/d3 when expe = 1: pe3/d3 when expe = 0: pe3 nc 69 d2 pe2/d2 pe2/d2 d2 pe2/d2 when expe = 1: pe2/d2 when expe = 0: pe2 nc 70 d1 pe1/d1 pe1/d1 d1 pe1/d1 when expe = 1: pe1/d1 when expe = 0: pe1 nc 71 d0 pe0/d0 pe0/d0 d0 pe0/d0 when expe = 1: pe0/d0 when expe = 0: pe0 nc 72 d15 d15 d15 d15 d15 when expe = 1: d15 when expe = 0: pd7 i/o7 73 d14 d14 d14 d14 d14 when expe = 1: d14 when expe = 0: pd6 i/o6 74 d13 d13 d13 d13 d13 when expe = 1: d13 when expe = 0: pd5 i/o5 75 d12 d12 d12 d12 d12 when expe = 1: d12 when expe = 0: pd4 i/o4 76 vss vss vss vss vss vss vss
15 pin name flash memory pin no. mode 1 mode 2 mode 4 mode 5 mode 6 mode 7 program- mer mode 77 d11 d11 d11 d11 d11 when expe = 1: d11 when expe = 0: pd3 i/o3 78 d10 d10 d10 d10 d10 when expe = 1: d10 when expe = 0: pd2 i/o2 79 d9 d9 d9 d9 d9 when expe = 1: d9 when expe = 0: pd1 i/o1 80 d8 d8 d8 d8 d8 when expe = 1: d8 when expe = 0: pd0 i/o0 81 p62/tmci0/ tend0 irq10 tend0 irq10 tend0 irq10 tend0 irq10 tend0 irq10 tend0 irq10 tend1 rq11 tend1 rq11 tend1 rq11 tend1 rq11 tend1 rq11 tend1 rq11 dack0 irq12 dack0 irq12 dack0 irq12 dack0 irq12 dack0 irq12 dack0 irq12 dack1 irq13 dack1 irq13 dack1 irq13 dack1 irq13 dack1 irq13 dack1 irq13 wait wait wait wait wait wait ucas irq14 ucas irq14 ucas irq14 ucas irq14 ucas irq14 ucas irq14 irq14
16 pin name flash memory pin no. mode 1 mode 2 mode 4 mode 5 mode 6 mode 7 program- mer mode 87 pf2/ lcas irq15 lcas irq15 lcas irq15 lcas irq15 lcas irq15 lcas irq15 irq15 lwr lwr lwr lwr lwr lwr hwr hwr hwr hwr hwr hwr rd rd rd rd rd rd as as as as as as res res res res res res res pf7/ pf7/ pf7/ pf7/ pf7/ nc 96 vcc vcc vcc vcc vcc vcc vcc 97 extal extal extal extal extal extal extal 98 xtal xtal xtal xtal xtal xtal xtal 99 vss vss vss vss vss vss vss 100 stby stby stby stby stby stby cs0 cs0 cs0 cs0 cs0 cs0 cs1 cs1 cs1 cs1 cs1 cs1
17 pin name flash memory pin no. mode 1 mode 2 mode 4 mode 5 mode 6 mode 7 program- mer mode 103 pg2/ cs2 cs2 cs2 cs2 cs2 cs2 cs3 cs3 cs3 cs3 cs3 cs3 cs4 cs4 cs4 cs4 cs4 cs4 cs5 cs5 cs5 cs5 cs5 cs5 irq0 irq0 irq0 irq0 irq0 irq0 irq1 irq1 irq1 irq1 irq1 irq1 irq2 irq2 irq2 irq2 irq2 irq2 adtrg irq3 adtrg irq3 adtrg irq3 adtrg irq3 adtrg irq3 adtrg irq3 cs6 irq6 cs6 irq6 cs6 irq6 cs6 irq6 cs6 irq6 cs6 irq6 irq6 cs7 oe irq7 cs7 oe irq7 cs7 oe irq7 cs7 oe irq7 cs7 oe irq7 cs7 oe irq7 irq7 breqo breqo breqo breqo breqo breqo
18 pin name flash memory pin no. mode 1 mode 2 mode 4 mode 5 mode 6 mode 7 program- mer mode 114 pg5/ back back back back back back breq breq breq breq breq breq irq4 irq4 irq4 irq4 irq4 irq4 irq5 irq5 irq5 irq5 irq5 irq5 irq6 irq6 irq6 irq6 irq6 irq6 irq7 irq7 irq7 irq7 irq7 irq7 oe oe oe oe oe oe
19 pin name flash memory pin no. mode 1 mode 2 mode 4 mode 5 mode 6 mode 7 program- mer mode 137 p32/rxd0/ irrxd p32/rxd0/ irrxd p32/rxd0/ irrxd p32/rxd0/ irrxd p32/rxd0/ irrxd p32/rxd0/ irrxd vcc 138 p31/txd1 p31/txd1 p31/txd1 p31/txd1 p31/txd1 p31/txd1 nc 139 p30/txd0/ irtxd p30/txd0/ irtxd p30/txd0/ irtxd p30/txd0/ irtxd p30/txd0/ irtxd p30/txd0/ irtxd nc 140 p80/ edreq2 irq0 edreq2 irq0 edreq2 irq0 edreq2 irq0 edreq2 irq0 edreq2 irq0 irq0 edreq3 irq1 edreq3 irq1 edreq3 irq1 edreq3 irq1 edreq3 irq1 edreq3 irq1 irq1 etend2 irq2 etend2 irq2 etend2 irq2 etend2 irq2 etend2 irq2 etend2 irq2 irq2
20 1.5 pin functions table 1.3 pin functions pin no. type symbol fp-144 i/o name and function power vcc 5, 39, 67, 96, 116 input power: for connection to the power supply. all v cc pins should be connected to the system power supply. vss 12, 19, 26, 47, 76, 99, 136 input ground: for connection to the power supply. all v ss pins should be connected to the system power supply (0 v). pllvcc 94 input pll power: the on-chip pll oscillator power supply. pllvss 92 input pll ground: the on-chip pll oscillator ground. clock xtal 98 input for connection to a crystal oscillator. see section 19, clock pulse generator, in the h8s/2678 series hardware manual for typical connection diagrams for a crystal oscillator and external clock input. extal 97 input for connection to a crystal oscillator. the extal pin can also input an external clock. see section 19, clock pulse generator, in the h8s/2678 series hardware manual for typical connection diagrams for a crystal oscillator and external clock input. 95 output system clock: supplies the system clock to external devices.
21 pin no. type symbol fp-144 i/o name and function operating mode control md2 to md0 1, 144, 143 input mode pins: these pins set the operating mode. the relation between the settings of pins md2 to md0 and the operating mode is shown below. these pins should not be changed while the mcu is operating. md0 md1 md0 operating mode 000 1 mode 1 1 0 mode 2 1 1 0 0 mode 4 1 mode 5 1 0 mode 6 1 mode 7 system control res reset input: when this pin is driven low, the chip is reset. stby standby: when this pin is driven low, a transition is made to hardware standby mode. breq bus request: requests chip to release the bus to an external bus master. breqo bus request output: external bus request signal used when an internal bus master accesses external space when the external bus is released. back bus request acknowledge: indicates that the bus has been released to an external bus master. fwe * 62 input flash write enable: enables/disables flash memory.
22 pin no. type symbol fp-144 i/o name and function interrupt signals nmi 38 input nonmaskable interrupt: requests a nonmaskable interrupt. fix high when not used. irq15 irq0 irq15 irq0 interrupt request 15 to 0: these pins request a maskable interrupt. address bus a23 to a0 32 to 27, 25 to 20, 18 to 13, 11 to 6 output address bus: these pins output an address. data bus d15 to d0 72 to 75, 77 to 80, 63 to 66, 68 to 71 input/ output data bus: these pins constitute a bidirectional data bus. bus control cs7 cs0 chip select: signals that select areas 7 to 0. as address strobe: when this pin is low, it indicates that address output on the address bus is valid. rd read: when this pin is low, it indicates that the external address space is being read. hwr high write/write enable: strobe signal indicating that external space is to be written, and the upper half (d15 to d8) of the data bus is enabled. write enable signal for dram interface space. lwr low write: strobe signal indicating that external space is to be written, and the lower half (d7 to d0) of the data bus is enabled.
23 pin no. type symbol fp-144 i/o name and function bus control ucas upper column address strobe: upper column address strobe signal for 16-bit dram interface space. column address strobe signal for 8-bit dram interface space. lcas lower column address strobe: lower column address strobe signal for 16-bit dram interface space. wait wait: requests insertion of a wait state in the bus cycle when accessing external 3-state address space. oe oe output enable: output enable signal for dram interface space. dma controller (dmac) dreq1 dreq0 dreq1 dreq0 dma transfer request 1, 0: these signals request dmac activation. tend1 tend0 tend1 tend0 dma transfer end 1, 0: these signals indicate the end of dmac data transfer. dack1 dack0 dack1 dack0 dma transfer acknowledge 1, 0: dmac single address transfer acknowledge signals. exdma controller (exdmac) edreq3 edreq0 exdma transfer request 3 to 0: these signals request exdmac activation. etend3 etend0 exdma transfer end 3 to 0: these signals indicate the end of exdmac data transfer. edack3 edack0 exdma transfer acknowledge 3 to 0: exdmac single address transfer acknowledge signals. edrak3 edrak0 edreq acknowledge 3 to 0: these signals notify an external device of acceptance and start of execution of an external request.
24 pin no. type symbol fp-144 i/o name and function 16-bit timer pulse unit (tpu) tclkd to tclka 51, 49, 46, 45 input clock input d to a: external clock input pins. tioca0, tiocb0, tiocc0, tiocd0 43 to 46 input/ output input capture/output compare match a0 to d0: tgr0a to tgr0d input capture input/output compare output/pwm output pins. tioca1, tiocb1 48, 49 input/ output input capture/output compare match a1, b1: tgr1a and tgr1b input capture input/output compare output/pwm output pins. tioca2, tiocb2 50, 51 input/ output input capture/output compare match a2, b2: tgr2a and tgr2b input capture input/output compare output/pwm output pins. tioca3, tiocb3, tiocc3, tiocd3 52 to 55 input/ output input capture/output compare match a3 to d3: tgr3a to tgr3d input capture input/output compare output/pwm output pins. tioca4, tiocb4 56, 57 input/ output input capture/output compare match a4, b4: tgr4a and tgr4b input capture input/output compare output/pwm output pins. tioca5, tiocb5 58, 59 input/ output input capture/output compare match a5, b5: tgr5a and tgr5b input capture input/output compare output/pwm output pins. programmable pulse generator (ppg) po15 to po0 51 to 48, 46 to 43, 59 to 52 output pulse output 15 to 0: pulse output pins. 8-bit timer tmo0, tmo1 83, 84 output compare match output: compare match output pins. tmci0, tmci1 81, 82 input counter external clock input: input pins for the external clock input to the counter. tmri0, tmri1 60, 61 input counter external reset input: counter reset input pins.
25 pin no. type symbol fp-144 i/o name and function watchdog timer (wdt) wdtovf watchdog timer overflow: counter overflow signal output pin in watchdog timer mode. serial communi- cation interface (sci)/smart card txd2, txd1, txd0/irtxd 107, 138, 139 output transmit data (channels 0, 1, 2): data output pins. interface (sci0 with irda function) rxd2, rxd1, rxd0/irrxd 108, 135, 137 input receive data (channels 0, 1, 2): data input pins. sck2, sck1, sck0 109, 133, 134 input/ output serial clock (channels 0, 1, 2): clock input/output pins. a/d converter an15 to an12, an7 to an0 130 to 127, 126 to 123, 120 to 117 input analog 15 to 12, 7 to 0: analog input pins. adtrg a/d conversion external trigger input: pin for input of an external trigger to start a/d conversion. d/a converter da3, da2, da1, da0 130, 129, 126, 125 output analog output: d/a converter analog output pins. a/d converter, d/a converter avcc 122 input the power supply pin for the a/d converter and d/a converter. when the a/d converter and d/a converter are not used, this pin should be connected to the system power supply (+3 v). avss 131 input the ground pin for the a/d converter and d/a converter. this pin should be connected to the system power supply (0 v). vref 121 input the reference voltage input pin for the a/d converter and d/a converter. when the a/d converter and d/a converter are not used, this pin should be connected to the system power supply (+3 v).
26 pin no. type symbol fp-144 i/o name and function i/o ports p17 to p10 51 to 48, 46 to 43 input/ output port 1: eight input/output pins. the direction of each pin can be selected in the port 1 data direction register (p1ddr). p27 to p20 59 to 52 input/ output port 2: eight input/output pins. the direction of each pin can be selected in the port 2 data direction register (p2ddr). p35 to p30 133 to 135, 137 to 139 input/ output port 3: six input/output pins. the direction of each pin can be selected in the port 3 data direction register (p3ddr). p47 to p40 126 to 123, 120 to 117 input port 4: eight input pins. p57 to p50 130 to 127, 110 to 107 input input/ output port 5: four input pins and four input/output pins. the direction of each input/output pin can be selected in the port 5 data direction register (p5ddr). p65 to p60 84 to 81, 61, 60 input/ output port 6: six input/output pins. the direction of each pin can be selected in the port 6 data direction register (p6ddr). p75 to p70 42 to 40, 36 to 34 input/ output port 7: six input/output pins. the direction of each pin can be selected in the port 7 data direction register (p7ddr). p85 to p80 4 to 2, 142 to 140 input/ output port 8: six input/output pins. the direction of each pin can be selected in the port 8 data direction register (p8ddr). pa7 to pa0 32 to 27, 25, 24 input/ output port a: eight input/output pins. the direction of each pin can be selected in the port a data direction register (paddr). pb7 to pb0 23 to 20, 18 to 15 input/ output port b: eight input/output pins. the direction of each pin can be selected in the port b data direction register (pbddr).
27 pin no. type symbol fp-144 i/o name and function i/o ports pc7 to pc0 14, 13, 11 to 6 input/ output port c: eight input/output pins. the direction of each pin can be selected in the port c data direction register (pcddr). pd7 to pd0 72 to 75, 77 to 80 input/ output port d: eight input/output pins. the direction of each pin can be selected in the port d data direction register (pdddr). pe7 to pe0 63 to 66, 68 to 71 input/ output port e: eight input/output pins. the direction of each pin can be selected in the port e data direction register (peddr). pf7 to pf0 95, 91 to 85 input/ output port f: eight input/output pins. the direction of each pin can be selected in the port f data direction register (pfddr). pg6 to pg0 115 to 113, 104 to 101 input/ output port g: seven input/output pins. the direction of each pin can be selected in the port g data direction register (pgddr). ph3 to ph0 112, 111, 106, 105 input/ output port h: four input/output pins. the direction of each pin can be selected in the port h data direction register (phddr). note: * f-ztat version only. in other versions, this is an nc pin.
28 1.6 product lineup table 1.4 h8s/2678 series product lineup product type model marking package (hitachi package code) h8s/2677 * 2 f-ztat version hd64f2677 hd64f2677vfc 144-pin plastic qfp (fp-144) h8s/2676 * 1 f-ztat version hd64f2676 hd64f2676vfc 144-pin plastic qfp (fp-144) mask rom version hd6432676 hd6432676fc h8s/2675 * 2 mask rom version hd6432675 hd6432675fc 144-pin plastic qfp (fp-144) h8s/2673 * 1 mask rom version hd6432673 HD6432673FC 144-pin plastic qfp (fp-144) h8s/2670 * 1 romless version hd6412670 hd6412670vfc 144-pin plastic qfp (fp-144) notes: 1. under development 2. in planning stage 1.7 package dimensions hitachi code jedec eiaj weight (reference value) fp-144g conforms 2.4 g unit: mm *dimension including the plating thickness base material dimension 0.10 m 20 22.0 8 0.10 1.25 0.20 figure 1.3 fp-144 package dimensions
29 section 2 mcu operating modes 2.1 overview 2.1.1 operating mode selection (f-ztat version) the h8s/2678 series f-ztat version has twelve operating modes (modes 1, 2, 4 to 7, and 10 to 15) that are selected by the flash write enable pin (fwe) and the mode pins (md2 to md0). the input at these pins determines the cpu operating mode and the initial bus width, as shown in table 2.1. table 2.1 lists the mcu operating modes.
30 table 2.1 mcu operating mode selection (f-ztat version) mcu cpu external data bus operating mode fwe md2 md1 md0 operating mode description on-chip rom initial width max. width 0 0000 1 1 advanced expanded mode with on-chip disabled 16 bits 16 bits 210 rom disabled 8 bits 16 bits 31 4 1 0 0 expanded mode with on-chip rom enabled enabled 8 bits 16 bits 5 1 external rom activation enabled 16 bits 16 bits 610 expanded mode with on-chip rom enabled 8 bits 16 bits 7 1 single-chip activation mode with on-chip rom enabled enabled 16 bits 8 1000 91 10 1 0 advanced boot mode enabled 8 bits 16 bits 11 1 12 1 0 0 advanced user program enabled 8 bits 16 bits 13 1 mode 16 bits 16 bits 14 1 0 advanced user program enabled 8 bits 16 bits 15 1 mode 16 bits
31 the cpu? architecture allows for 4 gigabytes of address space, but the h8s/2678 series chip actually accesses a maximum of 16 mbytes. modes 1, 2, and 4 to 6 are externally expanded modes that allow access to external memory and peripheral devices. the externally expanded modes allow switching between 8-bit and 16-bit bus modes. after program execution starts, an 8-bit or 16-bit address space can be set for each area, depending on the bus controller setting. if 16-bit access is selected for any one area, 16-bit bus mode is set; if 8- bit access is selected for all areas, 8-bit bus mode is set. pin functions depend on the operating mode. mode 7 is a single-chip activation externally expanded mode that allows access to external memory and peripheral devices to be switched at the start of program execution. in the single-chip activation externally expanded mode, it is possible to switch between externally expanded mode and single-chip mode by means of the expe bit in the system control register (syscr). immediately after a reset, the chip starts up in single-chip mode, but after the start of program execution, it is possible to change to externally expanded mode by setting expe accordingly. pin functions depend on the operating mode. modes 10 to 15 are boot modes and user program modes that allow programming and erasing of flash memory. for details see section 18, rom, in the h8s/2678 series hardware manual. the h8s/2678 series f-ztat version can be used only in modes 1, 2, 4 to 7, and 10 to 15. this means that the flash write enable pin and mode pins must be set to select one of these modes. do not change the inputs at the mode pins during operation. 2.1.2 operating mode selection (romless and mask rom versions) the h8s/2678 series romless and mask rom versions have six operating modes* (modes 1, 2, and 4 to 7) that are selected by the mode pins (md2 to md0). the input at these pins determines the cpu operating mode, enabling or disabling of on-chip rom, and the initial bus width, as shown in table 2.2. table 2.2 lists the mcu operating modes.
32 table 2.2 mcu operating mode selection* (romless and mask rom versions) mcu cpu external data bus operating mode md2 md1 md0 operating mode description on-chip rom initial width max. width 0 000 1 1 advanced expanded mode with on-chip disabled 16 bits 16 bits 210 rom disabled 8 bits 16 bits 31 4 1 0 0 advanced expanded mode with on-chip rom enabled enabled 8 bits 16 bits 5 1 external rom activation expanded mode 16 bits 16 bits 610 with on-chip rom enabled 8 bits 16 bits 7 1 single-chip activation mode with on-chip rom enabled 16 bits note: * only modes 1 and 2 are available in the romless version. the cpu? architecture allows for 4 gigabytes of address space, but the h8s/2678 series chip actually accesses a maximum of 16 mbytes. modes 1, 2, and 4 to 6 are externally expanded modes that allow access to external memory and peripheral devices. the externally expanded modes allow switching between 8-bit and 16-bit bus modes. after program execution starts, an 8-bit or 16-bit address space can be set for each area, depending on the bus controller setting. if 16-bit access is selected for any one area, 16-bit bus mode is set; if 8- bit access is selected for all areas, 8-bit bus mode is set. pin functions depend on the operating mode. in the single-chip activation externally expanded mode, it is possible to switch between externally expanded mode and single-chip mode. immediately after a reset, the chip starts up in single-chip mode, but after the start of program execution, it is possible to change to externally expanded mode by setting the expe bit in the system control register (syscr) accordingly. pin functions depend on the operating mode.
33 the h8s/2678 series mask rom version can be used only in modes 1, 2, and 4 to 7, and the romless version only in modes 1 and 2. this means that the mode pins must be set to select one of these modes. do not change the inputs at the mode pins during operation. 2.1.3 register configuration the h8s/2678 series has a mode control register (mdcr) that indicates the inputs at the mode pins (md2 to md0), and a system control register (syscr) that controls the operation of the chip. table 2.3 summarizes these registers. table 2.3 registers name abbreviation r/w initial value address * 1 mode control register mdcr r undefined h'ff3e system control register syscr r/w h'c1/h'c3 * 2 h'ff3d notes: 1. lower 16 bits of the address. 2. determined by pins md2 to md0. 2.2 register descriptions 2.2.1 mode control register (mdcr) bit 76543210 mds2 mds1 mds0 initial value 00000 * * * read/write r r r note: * determined by pins md2 to md0. mdcr is an 8-bit read-only register that monitors the current operating mode of the h8s/2678 series chip. bits 7 to 3?eserved: these bits are always read as 0 and cannot be modified. the write value should always be 1. bits 2 to 0?ode select 2 to 0 (md2 to md0): these bits indicate the input levels at pins md2 to md0 (the current operating mode). bits mds2 to mds0 correspond to pins md2 to md0. mds2 to mds0 are read-only bits?hey cannot be written to. the mode pin (md2 to md0) input levels are latched into these bits when mdcr is read. these latches are canceled by a reset.
34 2.2.2 system control register (syscr) bit 76543210 macs flshe expe rame initial value 110000 * 1 read/write r/w r/w r/w r/w r/w r/w r/w note: * determined by pins md2 to md0. bits 7 and 6?eserved: these are readable/writable bits, but the write value should always be 1. bit 5?ac saturation (macs): selects either saturating or non-saturating calculation for the mac instruction. bit 5 macs description 0 non-saturating calculation for mac instruction (initial value) 1 saturating calculation for mac instruction bit 4?eserved: this is a readable/writable bit, but the write value should always be 0. bit 3?lash memory control register enable (flshe): controls cpu access to the flash memory control registers (flmcr1, flmcr2, ebr1, and ebr2). for details see section 18, rom, in the h8s/2678 series hardware manual. in the mask rom and romless versions, 0 should be written to this bit. bit 3 flshe description 0 flash memory control registers are not selected for area h'ffffc8 to h'ffffcb (initial value) 1 flash memory control registers are selected for area h'ffffc8 to h'ffffcb bit 2?eserved: this bit is always read as 0 and cannot be modified. the write value should always be 0. bit 1?xternal bus mode enable (expe): sets external bus mode. in modes 1, 2, 4, 5, 6, 10, 12, 13, and 14, this bit is fixed at 1 and cannot be modified. in modes 7, 11, and 15, this bit has an initial value of 0, and can be read and written.
35 writing of 0 to expe when its value is 1 should only be carried out when an external bus cycle* is not being executed. note: * there are cases where external and internal bus cycles are executed in parallel due to the write data buffer function, the refresh control function, the exdmac, the bus-released state, and so forth. bit 1 expe description 0 external bus disabled 1 external bus enabled bit 0?am enable (rame): enables or disables the on-chip ram. the rame bit is initialized when the reset state is released. it is not initialized in software standby mode. bit 0 rame description 0 on-chip ram disabled 1 on-chip ram enabled (initial value) 2.3 operating mode descriptions 2.3.1 mode 1 (expanded mode with on-chip rom disabled) the cpu can access a 16-mbyte address space in advanced mode. the on-chip rom is disabled. ports a, b, and c function as an address bus, ports d and e function as a data bus, and parts of ports f and g carry bus control signals. the initial bus mode after a reset is 16 bits, with 16-bit access to all areas. however, if 8-bit access is designated for all areas by the bus controller, the bus mode switches to 8 bits. 2.3.2 mode 2 (expanded mode with on-chip rom disabled) this is an externally expanded mode with on-chip rom disabled. operation is the same as in mode 1, except that the initial external bus mode after a reset is 8 bits. 2.3.3 mode 3 this mode is not supported in the h8s/2678 series, and must not be selected.
36 2.3.4 mode 4 (expanded mode with on-chip rom enabled) the cpu can access a 16-mbyte address space in advanced mode. the on-chip rom is enabled. ports a, b, and c function as input ports immediately after a reset, but can be set to function as an address bus. for details see section 5, i/o ports. port d functions as a data bus, and parts of ports f and g carry bus control signals. the initial bus mode after a reset is 8 bits, with 8-bit access to all areas. the program in on-chip rom connected to the first half of area 0 is executed. however, if 16-bit access is designated for any area by the bus controller, the bus mode switches to 16 bits and port e functions as a data bus. 2.3.5 mode 5 (external rom activation expanded mode with on-chip rom enabled) the cpu can access a 16-mbyte address space in advanced mode. the on-chip rom* 1 is enabled. ports a, b, and c function as an address bus, ports d and e function as a data bus, and parts of ports f and g carry bus control signals. the initial bus mode after a reset is 16 bits, with 16-bit access to all areas. the program in on-chip rom* 2 connected to the first half of area 0 is executed. however, if 8-bit access is designated for any area by the bus controller, the bus mode switches to 8 bits. notes: 1. h8s/2678: h'100000 to h'180000; h8s/2675: h'100000 to h'140000 2. h8s/2678, h8s/2675: h'000000 to h'100000 2.3.6 mode 6 (external rom activation expanded mode with on-chip rom enabled) this is an external rom activation expanded mode with on-chip rom disabled. operation is the same as in mode 5, except that the initial external bus mode after a reset is 8 bits. 2.3.7 mode 7 (single-chip activation mode with on-chip rom enabled) the cpu can access a 16-mbyte address space in advanced mode. the on-chip rom is enabled, and the chip starts up in single-chip mode. external addresses cannot be used in single-chip mode, but they can be made accessible by means of a setting in the system control register (syscr). when external addresses are enabled, settings can be made to designate ports a, b, and c for address output, and ports d and e as data bus. for details see section 5, i/o ports. the initial mode after a reset is single-chip mode, with all i/o ports available for use as input/output ports. however, the mode can be switched to externally expanded mode by means of a setting in syscr. when externally expanded mode is selected, all areas are initially designated as 16-bit access space. the function of pins in ports a to h is the same as in externally expanded mode with on-chip rom enabled.
37 2.3.8 modes 8 and 9 [f-ztat version only] modes 8 and 9 are not supported in the h8s/2678 series, and must not be selected. 2.3.9 mode 10 [f-ztat version only] this is a flash memory boot mode. for details see section 18, rom, in the h8s/2678 series hardware manual. except for flash memory erasing and programming, operation is the same as in mode 4 (advanced expanded mode with on-chip rom enabled). 2.3.10 mode 11 this is a flash memory boot mode. for details see section 18, rom, in the h8s/2678 series hardware manual. except for flash memory erasing and programming, operation is the same as in mode 7 (advanced single-chip activation expanded mode with on-chip rom enabled). 2.3.11 mode 12 this is a flash memory user program mode. for details see section 18, rom, in the h8s/2678 series hardware manual. except for flash memory erasing and programming, operation is the same as in mode 4 (advanced expanded mode with on-chip rom enabled). 2.3.12 modes 13 and 14 [f-ztat version only] this is a flash memory user program mode. for details see section 18, rom, in the h8s/2678 series hardware manual. except for flash memory erasing and programming, operation is the same as in modes 5 and 6 (advanced external rom activation expanded mode with on-chip rom enabled). 2.3.13 mode 15 [f-ztat version only] this is a flash memory user program mode. for details see section 18, rom, in the h8s/2678 series hardware manual. except for flash memory erasing and programming, operation is the same as in mode 7 (advanced single-chip activation expanded mode with on-chip rom enabled).
38 2.4 pin functions in each operating mode the pin functions of ports a to h vary depending on the operating mode. table 2.4 shows their functions in each operating mode. table 2.4 pin functions in each operating mode port mode 1 mode 2 mode 4 mode 5 mode 6 mode 7 mode 10 mode 11 mode 12 mode 13 mode 14 mode 15 port a pa7 to pa5 p * /a p * /a p * /a p * /a p * /a p * /a p * /a p * /a p * /a p * /a p * /a p * /a pa4 to pa0 aa aa a a port b a a p * /aaap * /a p * /a p * /a p * /aaap * /a port c a a p * /aaap * /a p * /a p * /a p * /aaap * /a port d dddddp * /d d p * /ddddp * /d port e p/d * p * /d p/d * p/d * p * /d p * /d p * /d p * /d p * /d p/d * p * /d p * /d port f pf7, pf6 p/c * p/c * p/c * p/c * p/c * p * /c p * /c p * /c p/c * p/c * p/c * p * /c pf5, pf4 ccccc c ccc pf3 p/c * p/c * p/c * p/c * p/c * p/c * p/c * p/c * p/c * pf2 to pf0 p * /c p * /c p * /c p * /c p * /c p * /c p * /c p * /c p * /c port g pg7 to pg1 p * /c p * /c p * /c p * /c p * /c p * /c p * /c p * /c p * /c p * /c p * /c p * /c pg0 p/c * p/c * p * /c p/c * p/c * p/c * p * /c p/c * p/c * port h p * /c p * /c p * /c p * /c p * /c p * /c p * /c p * /c p * /c p * /c p * /c p * /c legend: p: i/o port a: address bus output d: data bus input/output c: control signals, clock input/output note: * after reset
39 2.5 memory map in each operating mode figures 2.1 to 2.13 show memory maps for each of the operating modes. the address space is 16 mbytes. the on-chip rom capacity is 384 kbytes in the h8s/2677, 256 kbytes in the h8s/2676, 128 kbytes in the h8s/2675, and 64 kbytes in the h8s/2673; the on-chip ram capacity is 8 kbytes. the address space is divided into eight areas. for details see section 4, bus controller. only advanced mode is supported in the h8s/2678 series.
40 modes 1 and 2 (expanded modes with on-chip rom disabled) mode 4 (expanded mode with on-chip rom enabled) h'000000 h'ffa000 h'ffc000 h'000000 h'ffa000 h'ffc000 h'fffc00 external address space on-chip ram/external address space * external address space internal i/o registers external address space internal i/o registers on-chip rom on-chip ram/external address space * external address space internal i/o registers external address space internal i/o registers h'ffffff h'fffc00 h'ffff00 h'ffff20 h'ffffff h'ffff00 h'ffff20 h'060000 external address space note: * external addresses can be accessed by clearing the rame bit in syscr to 0. figure 2.1 h8s/2677 memory map in each operating mode (1)
41 modes 5 and 6 (external rom activation expanded modes with on-chip rom enabled) mode 7 (single-chip activation expanded mode with on-chip rom enabled) h'000000 h'ffa000 h'ffc000 h'000000 h'ffa000 h'ffc000 h'fffc00 external address space on-chip ram/external address space * 1 external address space external address space internal i/o registers external address space internal i/o registers on-chip rom on-chip ram/external address space * 3 external address space/reserved area * 2 external address space/reserved area * 2 internal i/o registers internal i/o registers h'ffffff h'fffc00 h'ffff00 h'ffff20 h'ffffff h'ffff00 h'ffff20 h'060000 h'100000 h'160000 external address space/reserved area * 2 on-chip rom notes: 1. external addresses can be accessed by clearing the rame bit in syscr to 0. 2. when expe = 1, external address space; when expe = 0, reserved area. 3. when expe = 1, external address space when rame = 0, on-chip ram when rame = 1. when expe = 0, on-chip ram area. figure 2.2 h8s/2677 memory map in each operating mode (2)
42 mode 10 boot mode (expanded mode with on-chip rom enabled) mode 11 boot mode (single-chip activation expanded mode with on-chip rom enabled) h'000000 h'ffa000 h'ffc000 h'000000 h'ffa000 h'ffc000 h'fffc00 on-chip ram * 2 external address space external address space internal i/o registers external address space internal i/o registers on-chip rom on-chip ram * 2 external address space/reserved area * 1 external address space/reserved area * 1 internal i/o registers internal i/o registers h'ffffff h'fffc00 h'ffff00 h'ffff20 h'ffffff h'ffff00 h'ffff20 h'060000 h'060000 external address space/reserved area * 1 on-chip rom notes: 1. when expe = 1, external address space; when expe = 0, reserved area. 2. on-chip ram is used for flash memory programming. do not clear the rame bit in syscr to 0. figure 2.3 h8s/2677 memory map in each operating mode (3) [f-ztat version only]
43 mode 12 user program mode (expanded mode with on-chip rom enabled) mode 15 user program mode (single-chip activation expanded mode with on-chip rom enabled) h'000000 h'ffa000 h'ffc000 h'000000 h'ffa000 h'ffc000 h'fffc00 on-chip ram * 2 external address space external address space internal i/o registers external address space internal i/o registers on-chip rom on-chip ram * 2 external address space/reserved area * 1 external address space/reserved area * 1 internal i/o registers internal i/o registers h'ffffff h'fffc00 h'ffff00 h'ffff20 h'ffffff h'ffff00 h'ffff20 h'060000 h'060000 external address space/reserved area * 1 on-chip rom notes: 1. when expe = 1, external address space; when expe = 0, reserved area. 2. on-chip ram is used for flash memory programming. do not clear the rame bit in syscr to 0. modes 13 and 14 (external rom activation expanded modes with on-chip rom enabled) h'000000 h'ffa000 h'ffc000 external address space on-chip ram * 2 external address space external address space internal i/o registers external address space internal i/o registers h'ffffff h'fffc00 h'ffff00 h'ffff20 h'100000 h'160000 on-chip rom figure 2.4 h8s/2677 memory map in each operating mode (4) [f-ztat version only]
44 h'000000 h'ffa000 h'ffc000 h'000000 h'ffa000 h'ffc000 h'fffc00 external address space on-chip ram/external address space * external address space internal i/o registers external address space internal i/o registers on-chip rom on-chip ram/external address space * external address space internal i/o registers external address space internal i/o registers h'ffffff h'fffc00 h'ffff00 h'ffff20 h'ffffff h'ffff00 h'ffff20 h'040000 external address space modes 1 and 2 (expanded modes with on-chip rom disabled) mode 4 (expanded mode with on-chip rom enabled) note: * external addresses can be accessed by clearing the rame bit in syscr to 0. figure 2.5 h8s/2676 memory map in each operating mode (1)
45 h'000000 h'ffa000 h'ffc000 h'000000 h'ffa000 h'ffc000 h'fffc00 external address space on-chip ram/external address space * 1 external address space external address space internal i/o registers external address space internal i/o registers on-chip rom on-chip ram/external address space * 3 external address space/reserved area * 2 external address space/reserved area * 2 internal i/o registers internal i/o registers h'ffffff h'fffc00 h'ffff00 h'ffff20 h'ffffff h'ffff00 h'ffff20 h'040000 h'100000 h'140000 external address space/reserved area * 2 on-chip rom modes 5 and 6 (external rom activation expanded modes with on-chip rom enabled) mode 7 (single-chip activation expanded mode with on-chip rom enabled) notes: 1. external addresses can be accessed by clearing the rame bit in syscr to 0. 2. when expe = 1, external address space; when expe = 0, reserved area. 3. when expe = 1, external address space when rame = 0, on-chip ram when rame = 1. when expe = 0, on-chip ram area. figure 2.6 h8s/2676 memory map in each operating mode (2)
46 h'000000 h'ffa000 h'ffc000 h'000000 h'ffa000 h'ffc000 h'fffc00 on-chip ram * 2 external address space external address space internal i/o registers external address space internal i/o registers on-chip rom on-chip ram * 2 external address space/reserved area * 1 external address space/reserved area * 1 internal i/o registers internal i/o registers h'ffffff h'fffc00 h'ffff00 h'ffff20 h'ffffff h'ffff00 h'ffff20 h'040000 h'040000 external address space/reserved area * 1 on-chip rom mode 10 boot mode (expanded mode with on-chip rom enabled) mode 11 boot mode (single-chip activation expanded mode with on-chip rom enabled) notes: 1. when expe = 1, external address space; when expe = 0, reserved area. 2. on-chip ram is used for flash memory programming. do not clear the rame bit in syscr to 0. figure 2.7 h8s/2676 memory map in each operating mode (3) [f-ztat version only]
47 h'000000 h'ffa000 h'ffc000 h'000000 h'ffa000 h'ffc000 h'fffc00 on-chip ram * 2 external address space external address space internal i/o registers external address space internal i/o registers on-chip rom on-chip ram * 2 external address space/reserved area * 1 external address space/reserved area * 1 internal i/o registers internal i/o registers h'ffffff h'fffc00 h'ffff00 h'ffff20 h'ffffff h'ffff00 h'ffff20 h'040000 h'040000 external address space/reserved area * 1 on-chip rom mode 12 user program mode (expanded mode with on-chip rom enabled) mode 15 user program mode (single-chip activation expanded mode with on-chip rom enabled) notes: 1. when expe = 1, external address space; when expe = 0, reserved area. 2. on-chip ram is used for flash memory programming. do not clear the rame bit in syscr to 0. h'000000 h'ffa000 h'ffc000 external address space on-chip ram * 2 external address space external address space internal i/o registers external address space internal i/o registers h'ffffff h'fffc00 h'ffff00 h'ffff20 h'100000 h'140000 on-chip rom modes 13 and 14 (external rom activation expanded modes with on-chip rom enabled) figure 2.8 h8s/2676 memory map in each operating mode (4) [f-ztat version only]
48 h'000000 h'ffa000 h'ffc000 h'000000 h'ffa000 h'ffc000 h'fffc00 external address space on-chip ram/external address space * external address space internal i/o registers external address space internal i/o registers on-chip rom on-chip ram/external address space * external address space internal i/o registers external address space internal i/o registers h'ffffff h'fffc00 h'ffff00 h'ffff20 h'ffffff h'ffff00 h'ffff20 h'020000 external address space modes 1 and 2 (expanded modes with on-chip rom disabled) mode 4 (expanded mode with on-chip rom enabled) note: * external addresses can be accessed by clearing the rame bit in syscr to 0. figure 2.9 h8s/2675 memory map in each operating mode (1)
49 h'000000 h'ffa000 h'ffc000 h'000000 h'ffa000 h'ffc000 h'fffc00 external address space on-chip ram/external address space * 1 external address space external address space internal i/o registers external address space internal i/o registers on-chip rom on-chip ram/external address space * 3 external address space/reserved area * 2 external address space/reserved area * 2 internal i/o registers internal i/o registers h'ffffff h'fffc00 h'ffff00 h'ffff20 h'ffffff h'ffff00 h'ffff20 h'020000 h'100000 h'120000 external address space/reserved area * 2 on-chip rom modes 5 and 6 (external rom activation expanded modes with on-chip rom enabled) mode 7 (single-chip activation expanded mode with on-chip rom enabled) notes: 1. external addresses can be accessed by clearing the rame bit in syscr to 0. 2. when expe = 1, external address space; when expe = 0, reserved area. 3. when expe = 1, external address space when rame = 0, on-chip ram when rame = 1. when expe = 0, on-chip ram area. figure 2.10 h8s/2675 memory map in each operating mode (2)
50 h'000000 h'ffa000 h'ffc000 h'000000 h'ffa000 h'ffc000 h'fffc00 external address space on-chip ram/external address space * external address space internal i/o registers external address space internal i/o registers on-chip rom on-chip ram/external address space * external address space internal i/o registers external address space internal i/o registers h'ffffff h'fffc00 h'ffff00 h'ffff20 h'ffffff h'ffff00 h'ffff20 h'010000 external address space modes 1 and 2 (expanded modes with on-chip rom disabled) mode 4 (expanded mode with on-chip rom enabled) note: * external addresses can be accessed by clearing the rame bit in syscr to 0. figure 2.11 h8s/2673 memory map in each operating mode (1)
51 h'000000 h'ffa000 h'ffc000 h'000000 h'ffa000 h'ffc000 h'fffc00 external address space on-chip ram/external address space * 1 external address space external address space internal i/o registers external address space internal i/o registers on-chip rom on-chip ram/external address space * 3 external address space/reserved area * 2 external address space/reserved area * 2 internal i/o registers internal i/o registers h'ffffff h'fffc00 h'ffff00 h'ffff20 h'ffffff h'ffff00 h'ffff20 h'010000 h'100000 h'110000 external address space/reserved area * 2 on-chip rom modes 5 and 6 (external rom activation expanded modes with on-chip rom enabled) mode 7 (single-chip activation expanded mode with on-chip rom enabled) notes: 1. external addresses can be accessed by clearing the rame bit in syscr to 0. 2. when expe = 1, external address space; when expe = 0, reserved area. 3. when expe = 1, external address space when rame = 0, on-chip ram when rame = 1. when expe = 0, on-chip ram area. figure 2.12 h8s/2673 memory map in each operating mode (2)
52 h'000000 h'ffa000 h'ffc000 external address space on-chip ram/external address space * external address space internal i/o registers external address space internal i/o registers h'ffffff h'fffc00 h'ffff00 h'ffff20 modes 1 and 2 (expanded modes with on-chip rom disabled) note: * external addresses can be accessed by clearing the rame bit in syscr to 0. figure 2.13 h8s/2670 memory map in each operating mode
53 section 3 exception handling and interrupt controller 3.1 overview 3.1.1 exception handling types and priority as table 3.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. exception handling is prioritized as shown in table 3.1. if two or more exceptions occur simultaneously, they are accepted and processed in order of priority. trap instruction exceptions are accepted at all times in the program execution state. exception handling sources, the stack structure, and the operation of the cpu vary depending on the interrupt control mode set by the intm0 and intm1 bits in intcr. for details of exception handling and the interrupt controller, see section 2, exception handling, and section 3, interrupt controller, in the h8s/2678 series hardware manual. table 3.1 exception types and priority priority exception type start of exception handling high reset starts after a low-to-high transition at the res pin, or when the watchdog timer overflows trace * 1 starts when execution of the current instruction or exception handling ends, if the trace (t) bit is set to 1 interrupt starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued * 2 low trap instruction * 3 (trapa) started by execution of a trap instruction (trapa) notes: 1. traces are enabled only in interrupt control mode 2. trace exception handling is not executed after execution of an rte instruction. 2. interrupt detection is not performed on completion of andc, orc, xorc, or ldc instruction execution, or on completion of reset exception handling. 3. trap instruction exception handling requests are accepted at all times in the program execution state.
54 3.2 interrupt controller 3.2.1 interrupt controller features ? two interrupt control modes ? either of two interrupt control modes can be set by means of the intm1 and intm0 bits in the interrupt control register (intcr). ? priorities settable with iprs ? interrupt priority registers (iprs) are provided for setting interrupt priorities. eight priority levels can be set for each module for all interrupts except nmi. ? nmi is assigned the highest priority level of 8, and can be accepted at all times. ? independent vector addresses ? all interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. ? seventeen external interrupt pins ? nmi is the highest-priority interrupt, and is accepted at all times. rising edge or falling edge can be selected for nmi. ? falling edge, rising edge, or both edge detection, or level sensing, can be selected independently for irq15 to irq0. ? dtc and dmac control ? dtc and dmac activation is controlled by means of interrupts.
55 3.2.2 block diagram figure 3.1 shows a block diagram of the interrupt controller. intcr nmi input irq input internal interrupt sources swdtend to tei intm1 intm0 nmieg nmi input unit irq input unit isr iscr itsr ier ipr interrupt controller priority determination interrupt request vector number i i2 to i0 ccr exr cpu legend iscr: irq sense control register ier: irq enable register isr: irq status register ipr: interrupt priority register intcr: interrupt control register itsr: irq pin select register figure 3.1 block diagram of interrupt controller
56 3.2.3 pin configuration table 3.2 summarizes the interrupt controller pins. table 3.2 interrupt controller pins name abbreviation i/o function nonmaskable interrupt nmi input nonmaskable external interrupt; rising or falling edge can be selected external interrupt request 15 to 0 irq15 to irq0 input maskable external interrupts; rising, falling, or both edges, or level sensing, can be selected
57 3.2.4 register configuration table 3.3 summarizes the registers of the interrupt controller. table 3.3 interrupt controller registers name abbreviation r/w initial value address * 1 interrupt control register intcr r/w h'00 h'ff31 irq sense control register h iscrh r/w h'0000 h'fe1a irq sense control register l iscrl r/w h'0000 h'fe1c irq enable register ier r/w h'0000 h'ff32 irq status register isr r/(w) * 2 h'0000 h'ff34 irq pin select register itsr r/w h'0000 h'fe16 software standby release irq enable register ssier r/w h'0007 h'fe18 interrupt priority register a ipra r/w h'7777 h'fe00 interrupt priority register b iprb r/w h'7777 h'fe02 interrupt priority register c iprc r/w h'7777 h'fe04 interrupt priority register d iprd r/w h'7777 h'fe06 interrupt priority register e ipre r/w h'7777 h'fe08 interrupt priority register f iprf r/w h'7777 h'fe0a interrupt priority register g iprg r/w h'7777 h'fe0c interrupt priority register h iprh r/w h'7777 h'fe0e interrupt priority register i ipri r/w h'7777 h'fe10 interrupt priority register j iprj r/w h'7777 h'fe12 interrupt priority register k iprk r/w h'7777 h'fe14 notes: 1. lower 16 bits of the address. 2. only 0 can be written, to clear flags.
58 3.3 register descriptions 3.3.1 interrupt control register (intcr) bit 76543210 intm1 intm0 nmieg initial value 00000000 read/write r/w r/w r/w intcr is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for nmi. intcr is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 and 6?eserved: these bits are always read as 0 and cannot be modified. bits 5 and 4?nterrupt control mode 1 and 0 (intm1, intm0): these bits select either of two interrupt control modes for the interrupt controller. bit 5 intm1 bit 4 intm0 interrupt control mode description 0 0 0 interrupts are controlled by i bit (initial value) 1 setting prohibited 1 0 2 interrupts are controlled by bits i2 to i0, and ipr 1 setting prohibited bit 3?mi edge select (nmieg): selects the input edge for the nmi pin. bit 3 nmieg description 0 interrupt request generated at falling edge of nmi input (initial value) 1 interrupt request generated at rising edge of nmi input bits 2 to 0?eserved: these bits are always read as 0 and cannot be modified.
59 3.3.2 interrupt priority registers a to k (ipra to iprk) bit 15 14 13 12 11 10 9 8 ipr14 ipr13 ipr12 ipr10 ipr9 ipr8 initial value 01110111 read/write r/w r/w r/w r/w r/w r/w bit 76543210 ipr6 ipr5 ipr4 ipr2 ipr1 ipr0 initial value 01110111 read/write r/w r/w r/w r/w r/w r/w the ipr registers are eleven 16-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than nmi. the correspondence between interrupt sources and ipr settings is shown in table 3.4. the ipr registers set a priority (level 7 to 0) for each interrupt source other than nmi. the ipr registers are initialized to h'7777 by a reset and in hardware standby mode. bits 15, 11, 7, and 3?eserved: these bits are always read as 0 and cannot be modified. table 3.4 correspondence between interrupt sources and ipr settings register bits 14 to 12 bits 10 to 8 bits 6 to 4 bits 2 to 0 ipra irq0 irq1 irq2 irq3 iprb irq4 irq5 irq6 irq7 iprc irq8 irq9 irq10 irq11 iprd irq12 irq13 irq14 irq15 ipre dtc interval timer * refresh timer iprf * a/d converter tpu channel 0 tpu channel 1 iprg tpu channel 2 tpu channel 3 tpu channel 4 tpu channel 5 iprh 8-bit timer channel 0 8-bit timer channel 1 dmac exdmac channel 0 ipri exdmac channel 1 exdmac channel 2 exdmac channel 3 sci channel 0 iprj sci channel 1 sci channel 2 * * iprk * * * * note: * reserved bits. these bits are read as h'7, and the write value should be h'7.
60 as shown in table 3.4, multiple interrupts are assigned to one ipr. setting a value in the range from h'0 to h'7 in the 3-bit groups of bits 14 to 12, 10 to 8, 6 to 4, and 2 to 0 sets the priority of the corresponding interrupt. the lowest priority level, level 0, is assigned by setting h'0, and the highest priority level, level 7, by setting h'7. when interrupt requests are generated, the highest-priority interrupt according to the priority levels set in the ipr registers is selected. this interrupt level is then compared with the interrupt mask level set by the interrupt mask bits (i2 to i0) in the extend register (exr) in the cpu, and if the priority level of the interrupt is higher than the set mask level, an interrupt request is issued to the cpu. 3.3.3 irq enable register (ier) bit 15 14 13 12 11 10 9 8 irq15e irq14e irq13e irq12e irq11e irq10e irq9e irq8e initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w bit 76543210 irq7e irq6e irq5e irq4e irq3e irq2e irq1e irq0e initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w ier is a 16-bit readable/writable register that controls enabling and disabling of interrupt requests irq15 to irq0. ier is initialized to h'0000 by a reset and in hardware standby mode. bits 15 to 0?rq15 to irq0 enable (irq15e to irq0e): these bits select whether interrupts irq15 to irq0 are enabled or disabled. bit n irqne description 0 irqn interrupts disabled (initial value) 1 irqn interrupts enabled (n = 15 to 0)
61 3.3.4 irq sense control registers h and l (iscrh, iscrl) iscrh bit 15 14 13 12 11 10 9 8 irq15scb irq15sca irq14scb irq14sca irq13scb irq13sca irq12scb irq12sca initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w bit 76543210 irq11scb irq11sca irq10scb irq10sca irq9scb irq9sca irq8scb irq8sca initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w iscrl bit 15 14 13 12 11 10 9 8 irq7scb irq7sca irq6scb irq6sca irq5scb irq5sca irq4scb irq4sca initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w bit 76543210 irq3scb irq3sca irq2scb irq2sca irq1scb irq1sca irq0scb irq0sca initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w the iscr registers are two 16-bit readable/writable registers that select rising edge, falling edge, or both edge detection, or level sensing, for the input at pins irq15 to irq0 . the iscr registers are initialized to h'0000 by a reset and in hardware standby mode.
62 bits 15 to 0?rq15 sense control a and b (irq15sca, irq15scb) to irq0 sense control a and b (irq0sca, irq0scb) irqnscb irqnsca description 0 0 interrupt request generated at irqn input low level (initial value) 1 interrupt request generated at falling edge of irqn input 1 0 interrupt request generated at rising edge of irqn input 1 interrupt request generated at both falling and rising edges of irqn input (n = 15 to 0) 3.3.5 irq status register (isr) bit 15 14 13 12 11 10 9 8 irq15f irq14f irq13f irq12f irq11f irq10f irq9f irq8f initial value 00000000 read/write r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * bit 76543210 irq7f irq6f irq5f irq4f irq3f irq2f irq1f irq0f initial value 00000000 read/write r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * note: * only 0 can be written, to clear the flag. isr is a 16-bit readable/writable register that indicates the status of irq15 to irq0 interrupt requests. isr is initialized to h'0000 by a reset and in hardware standby mode. as irqnf may be set to 1 depending on the pin states after a reset, it is necessary to read isr, and then write 0s to it, following a reset.
63 bits 15 to 0?rq15 to irq0 flags (irq15f to irq0f): these bits indicate the status of irq15 to irq0 interrupt requests. bit n irqnf description 0 [clearing conditions] (initial value) ? when 0 is written to irqnf after reading irqnf = 1 ? when interrupt exception handling is executed when low-level detection is set (irqnscb = irqnsca = 0) and irqn input is high ? when irqn interrupt exception handling is executed when falling, rising, or both- edge detection is set (irqnscb = 1 or irqnsca = 1) ? when the dtc is activated by an irqn interrupt and the disel bit in mrb of the dtc is 0 1 [setting conditions] ? when irqn input goes low when low-level detection is set (irqnscb = irqnsca = 0) ? when a falling edge occurs in irqn input when falling edge detection is set (irqnscb = 0, irqnsca = 1) ? when a rising edge occurs in irqn input when rising edge detection is set (irqnscb = 1, irqnsca = 0) ? when a falling or rising edge occurs in irqn input when both-edge detection is set (irqnscb = irqnsca = 1) (n = 15 to 0)
64 3.3.6 irq pin select register (itsr) bit 15 14 13 12 11 10 9 8 its15 its14 its13 its12 its11 its10 its9 its8 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w bit 76543210 its7 its6 its5 its4 its3 its2 its1 its0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w itsr is a 16-bit readable/writable register that selects input pins irq15 to irq0. itsr is initialized to h'0000 by a reset and in hardware standby mode. bits 15 to 0?rq input pin select (its15 to its0): irqn input pins can be used as the pins shown below according to the value of itsn. (n = 15 to 0) bit its = 0 (initial value) its = 1 its15 pf2 p27 its14 pf1 p26 its13 p65 p25 its12 p64 p24 its11 p63 p23 its10 p62 p22 its9 p61 p21 its8 p60 p20 its7 p57 ph3 its6 p56 ph2 its5 p55 p85 its4 p54 p84 its3 p53 p83 its2 p52 p82 its1 p51 p81 its0 p50 p80
65 when an itsr setting is changed, if the selected pin level before the change is different from the selected pin level after the change, an edge may be generated internally and irqnf (n = 0 to 15) in isr may be set at an unintended timing. if the irqn interrupt (n = 0 to 15) is enabled at this time, the associated interrupt exception handling will be executed. to prevent unintended interrupts, make changes to itsr settings with irqn interrupts (n = 0 to 15) disabled, and then clear irqnf (n = 0 to 15). 3.3.7 software standby release irq enable register (ssier) bit 15 14 13 12 11 10 9 8 ssi15 ssi14 ssi13 ssi12 ssi11 ssi10 ssi9 ssi8 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w bit 76543210 ssi7 ssi6 ssi5 ssi4 ssi3 ssi2 ssi1 ssi0 initial value 00000111 read/write r/w r/w r/w r/w r/w r/w r/w r/w ssier is a 16-bit readable/writable register that selects the irq pins used to recover from the software standby state. ssier is initialized to h'0007 by a reset and in hardware standby mode. an irq interrupt used to recover from the software standby state must not be set as a dtc activation source. bits 15 to 0?oftware standby release irq setting (ssi15 to ssi0): these bits select the irq pins used to recover from the software standby state. bit n ssin description 0 irqn requests are not sampled in the software standby state (initial value when n = 15 to 3) 1 when an irqn request occurs in the software standby state, the chip recovers from the software standby state after the elapse of the oscillation settling time (initial value when n = 2 to 0)
66 3.4 interrupt sources interrupt sources comprise external interrupts (nmi and irq15 to irq0) and internal interrupts (56 sources). 3.4.1 external interrupts there are 17 external interrupt sources: nmi and irq15 to irq0. setting an ssi bit to 1 in ssier enables the corresponding irq15?rq0 interrupt to be used as a software standby mode release source. nmi interrupt: nmi is the highest-priority interrupt, and is always accepted by the cpu regardless of the interrupt control mode and the status of the cpu interrupt mask bits. the nmieg bit in intcr specifies whether an interrupt is requested at a rising edge or a falling edge on the nmi pin. the vector number for nmi interrupt exception handling is 7. irq15 to irq0 interrupts: interrupts irq15 to irq0 are requested by an input signal at pins irq15 to irq0 . interrupts irq15 to irq0 have the following features: ? using iscr, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins irq15 to irq0 . ? enabling or disabling of interrupt requests irq15 to irq0 can be selected with ier. ? the interrupt priority level can be set with ipr. ? the status of interrupt requests irq15 to irq0 is indicated in isr. isr flags can be cleared to 0 by software. a block diagram of interrupts irq15 to irq0 is shown in figure 3.2. irqn interrupt request irqne irqnf s r q clear signal edge/ level detection circuit irqnsca, irqnscb irqn figure 3.2 block diagram of interrupts irq15 to irq0
67 figure 3.3 shows the timing of the setting of irqnf. irqn figure 3.3 timing of setting of irqnf the vector numbers for irq15 to irq0 interrupt exception handling are 31 to 16. detection of irq15 to irq0 interrupts does not depend on whether the relevant pin has been set for input or output. when a pin is used as an external interrupt input pin, clear the corresponding ddr bit to 0 and do not use the pin as an i/o pin for another function. when interrupt request generation by a low level at the irq pin is selected for an irq15 to irq0 interrupt by means of an iscr setting, when an interrupt is requested the relevant irq pin should be held low until interrupt handling starts. the irq pin should then be returned to the high level, and irqnf (n = 0 to 15) cleared, in the interrupt handling routine. if the irq pin is returned to the high level before interrupt handling is started, the associated interrupt may not be executed. 3.4.2 internal interrupts there are 56 sources for internal interrupts from on-chip supporting modules. 1. for each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. if any one of these is set to 1, an interrupt request is issued to the interrupt controller. 2. the interrupt priority level can be set by means of ipr. 3. the dmac and dtc can be activated by a tpu, sci, or other interrupt request. when the dmac or dtc is activated by an interrupt, the interrupt control mode and cpu interrupt mask bits have no effect.
68 3.4.3 interrupt vector table table 3.5 shows interrupt exception handling sources, their vector addresses, and their priority order. in the default priority order, smaller vector numbers have higher priority. priorities among modules can be set by means of ipr. the priority order when two or more modules are set to the same priority, and the priority order within a module, are fixed as shown in table 3.5.
69 table 3.5 interrupt sources, vector addresses, and priority order interrupt source origin of interrupt source vector number vector address * ipr priority dtc activa- tion dmac activa- tion power-on reset 0 h'0000 high reserved 1 h'0004 reserved for system 2 h'0008 3 h'000c 4 h'0010 trace 5 h'0014 reserved for system 6 h'0018 nmi external pin 7 h'001c trap instruction 8 h'0020 (4 sources) 9 h'0024 10 h'0028 11 h'002c reserved for system 12 h'0030 13 h'0034 14 h'0038 irq0 external 16 h'0040 ipra14 ipra12 irq1 pin 17 h'0044 ipra10 ipra8 irq2 18 h'0048 ipra6 ipra4 irq3 19 h'004c ipra2 ipra0 irq4 20 h'0050 iprb14 iprb12 irq5 21 h'0054 iprb10 iprb8 irq6 22 h'0058 iprb6 iprb4 irq7 23 h'005c iprb2 iprb0 irq8 24 h'0060 iprc14 iprc12 irq9 25 h'0064 iprc10 iprc8 irq10 26 h'0068 iprc6 iprc4 irq11 27 h'006c iprc2 iprc0 irq12 28 h'0070 iprd14 iprd12 irq13 29 h'0074 iprd10 iprd8 irq14 30 h'0078 iprd6 iprd4 irq15 31 h'007c iprd2 iprd0 low
70 interrupt source origin of interrupt source vector number vector address * ipr priority dtc activa- tion dmac activa- tion swdtend (software- activated data transfer end) dtc 32 h'0080 ipre14 ipre12 high wovi (interval timer) watchdog timer 33 h'0084 ipre10 ipre8 reserved 34 h'0088 ipre6 ipre4 cmi (compare match) refresh controller 35 h'008c ipre2 ipre0 reserved 36 h'0090 iprf14 iprf12 37 h'0094 adi (a/d conversion end) a/d 38 h'0098 iprf10 iprf8 reserved 39 h'009c tgi0a (tgr0a input capture/compare match) tpu channel 0 40 h'00a0 iprf6 iprf4 tgi0b (tgr0b input capture/compare match) 41 h'00a4 tgi0c (tgr0c input capture/compare match) 42 h'00a8 tgi0d (tgr0d input capture/compare match) 43 h'00ac tci0v (overflow 0) 44 h'00b0 reserved 45 h'00b4 46 h'00b8 47 h'00bc tgi1a (tgr1a input capture/compare match) tpu channel 1 48 h'00c0 iprf2 iprf0 tgi1b (tgr1b input capture/compare match) 49 h'00c4 tci1v (overflow 1) 50 h'00c8 tci1u (underflow 1) 51 h'00cc tgi2a (tgr2a input capture/compare match) tpu channel 2 52 h'00d0 iprg14 iprg12 tgi2b (tgr2b input capture/compare match) 53 h'00d4 tci2v (overflow 2) 54 h'00d8 tci2u (underflow 2) 55 h'00dc low
71 interrupt source origin of interrupt source vector number vector address * ipr priority dtc activa- tion dmac activa- tion tgi3a (tgr3a input capture/compare match) tpu channel 3 56 h'00e0 iprg10 iprg8 high tgi3b (tgr3b input capture/compare match) 57 h'00e4 tgi3c (tgr3c input capture/compare match) 58 h'00e8 tgi3d (tgr3d input capture/compare match) 59 h'00ec tci3v (overflow 3) 60 h'00f0 reserved 61 h'00f4 62 h'00f8 63 h'00fc tgi4a (tgr4a input capture/compare match) tpu channel 4 64 h'0100 iprg6 iprg4 tgi4b (tgr4b input capture/compare match) 65 h'0104 tci4v (overflow 4) 66 h'0108 tci4u (underflow 4) 67 h'010c tgi5a (tgr5a input capture/compare match) tpu channel 5 68 h'0110 iprg2 iprg0 tgi5b (tgr5b input capture/compare match) 69 h'0114 tci5v (overflow 5) 70 h'0118 tci5u (underflow 5) 71 h'011c cmia0 (compare match a) 8-bit timer 72 h'0120 iprh14 iprh12 cmib0 (compare match b) channel 0 73 h'0124 ovi0 (overflow 0) 74 h'0128 reserved 75 h'012c cmia1 (compare match a) 8-bit timer 76 h'0130 iprh10 iprh8 cmib1 (compare match b) channel 1 77 h'0134 ovi1 (overflow 1) 78 h'0138 reserved 79 h'013c low
72 interrupt source origin of interrupt source vector number vector address * ipr priority dtc activa- tion dmac activa- tion dmtend0a (channel 0/channel 0a transfer end) dmac 80 h'0140 iprh6 iprh4 high dmtend0b (channel 0b transfer end) 81 h'0144 dmtend1a (channel 1/channel 1a transfer end) 82 h'0148 dmtend1b (channel 1b transfer end) 83 h'014c exdmtend0 (channel 0 transfer end) exdmac 84 h'0150 iprh2 iprh0 exdmtend1 (channel 1 transfer end) 85 h'0154 ipri14 ipri12 exdmtend2 (channel 2 transfer end) 86 h'0158 ipri10 ipri8 exdmtend3 (channel 3 transfer end) 87 h'015c ipri6 ipri4 eri0 (receive error 0) sci 88 h'0160 ipri2 ipri0 rxi0 (receive completed 0) channel 0 89 h'0164 txi0 (transmit data empty 0) 90 h'0168 tei0 (transmit end 0) 91 h'016c eri1 (receive error 1) sci 92 h'0170 iprj14 iprj12 rxi1 (receive completed 1) channel 1 93 h'0174 txi1 (transmit data empty 1) 94 h'0178 tei1 (transmit end 1) 95 h'017c eri2 (receive error 2) sci 96 h'0180 iprj10 iprj8 rxi2 (receive completed 2) channel 2 97 h'0184 txi2 (transmit data empty 2) 98 h'0188 tei2 (transmit end 2) 99 h'018c low
73 interrupt source origin of interrupt source vector number vector address * ipr priority dtc activa- tion dmac activa- tion reserved 100 h'0190 iprj6 iprj4 high 101 h'0194 102 h'0198 103 h'019c 104 h'01a0 iprj2 iprj0 105 h'01a4 106 h'01a8 107 h'01ac 108 h'01b0 iprk14 iprk12 109 h'01b4 110 h'01b8 111 h'01bc 112 h'01c0 iprk10 iprk8 113 h'01c4 114 h'01c8 115 h'01cc 116 h'01d0 iprk6 iprk4 117 h'01d4 118 h'01d8 119 h'01dc 120 h'01e0 iprk2 iprk2 121 h'01e4 122 h'01e8 123 h'01ec 124 h'01f0 125 h'01f4 126 h'01f8 127 h'01fc low notes: interrupt sources vary depending on the model. see the reference manual for the relevant model for details. * lower 16 bits of the start address.
74 3.5 interrupt operation 3.5.1 interrupt control modes and interrupt operation interrupt operations in the h8s/2678 series differ depending on the interrupt control mode. nmi interrupts are accepted at all times except in the reset state and the hardware standby state. in the case of irq interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt. clearing an enable bit to 0 disables the corresponding interrupt request. interrupt sources for which the enable bits are set to 1 are controlled by the interrupt controller. table 3.6 shows the interrupt control modes. the interrupt controller performs interrupt control according to the interrupt control mode set by the intm1 and intm0 bits in intcr, the priorities set in ipr, and the masking state indicated by the i bit in the cpu? ccr, and bits i2 to i0 in exr. table 3.6 interrupt control modes interrupt intcr priority control mode intm1 intm0 setting registers interrupt mask bits description 000 i interrupt mask control is performed by the i bit. 1 setting prohibited 2 1 0 ipr i2 to i0 8-level interrupt mask control is performed by bits i2 to i0. 8 priority levels can be set with ipr. 1 setting prohibited
75 figure 3.4 shows a block diagram of the priority decision circuit. 8-level mask control interrupt source interrupt control mode 0 i interrupt acceptance control default priority determination vector number i2 to i0 ipr interrupt control mode 2 figure 3.4 block diagram of interrupt control operation interrupt acceptance control: in interrupt control mode 0, interrupt acceptance control is performed by means of the i bit in ccr. table 3.7 shows the interrupts that can be selected in each interrupt control mode. table 3.7 interrupts selected in each interrupt control mode (1) interrupt mask bit interrupt control mode i selected interrupts 0 0 all interrupts 1 nmi interrupt 2 * all interrupts * : don t care
76 8-level control: in interrupt control mode 2, 8-level mask level determination is performed according to the interrupt priority level (ipr) for interrupts selected in interrupt acceptance control. the interrupt source selected is the interrupt with the highest priority level, and for which the priority level set in ipr is higher than the mask level. table 3.8 interrupts selected in each interrupt control mode (2) interrupt control mode selected interrupts 0 all interrupts 2 highest-priority-level (ipr) interrupt whose priority level is greater than the mask level (ipr > i2 to i0) default priority determination: when an interrupt is selected by 8-level control, its priority is determined and a vector number is generated. if the same value is set for ipr, acceptance of multiple interrupts is enabled, and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated. interrupt sources with a lower priority than the accepted interrupt source are held pending. table 3.9 shows operations and control signal functions in each interrupt control mode. table 3.9 operations and control signal functions in each interrupt control mode interrupt setting interrupt acceptance control 8-level control default priority t control mode intm1 intm0 i i2?0 ipr determination (trace) 0 0 0 o im x * 2 o 210x * 1 oim pr o t legend o: interrupt operation control performed x: no operation (all interrupts enabled) im: used as interrupt mask bit pr: sets priority. : not used. notes: 1. set to 1 when interrupt is accepted. 2. keep the initial setting (ipr writes prohibited).
77 3.5.2 interrupt control mode 0 enabling and disabling of irq interrupts and on-chip supporting module interrupts can be set by means of the i bit in the cpu? ccr. interrupts are enabled when the i bit is cleared to 0, and disabled when the i bit is set to 1. figure 3.5 shows a flowchart of the interrupt acceptance operation in this case. 1. if an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. the i bit is then referenced. if the i bit is cleared to 0, the interrupt request is accepted. if the i bit is set to 1, only an nmi interrupt is accepted, and other interrupt requests are held pending. 3. interrupt requests are sent to the interrupt controller, the highest-priority interrupt according to the priority order is selected, and the others are held pending. 4. when an interrupt request is accepted, processing for the instruction being executed at that time is completed before interrupt exception handling is started. 5. pc and ccr are saved to the stack area in interrupt exception handling. the pc value saved on the stack shows the address of the first instruction to be executed after returning from the interrupt service routine. 6. next, the i bit in ccr is set to 1. this masks all interrupts except nmi. 7. a vector address is generated for the accepted interrupt, and execution of the interrupt service routine starts at the address indicated by the contents of that vector address.
78 program execution state interrupt generated? nmi? irq0? irq1? tei2? i = 0? save pc and ccr i figure 3.5 flowchart of procedure up to interrupt acceptance in interrupt control mode 0
79 3.5.3 interrupt control mode 2 eight-level masking is implemented for irq interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits i2 to i0 of exr in the cpu with ipr. figure 3.6 shows a flowchart of the interrupt acceptance operation in this case. 1. if an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. when interrupt requests are sent to the interrupt controller, the interrupt with the highest priority level according to the interrupt priority levels set in ipr is selected, and lower-priority interrupt requests are held pending. if a number of interrupt requests with the same priority are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 3.4 is selected. 3. next, the priority of the selected interrupt request is compared with the interrupt mask level set in exr. an interrupt request with a priority no higher than the mask level set at that time is held pending, and only an interrupt request with a priority higher than the interrupt mask level is accepted. 4. when an interrupt request is accepted, processing for the instruction being executed at that time is completed before interrupt exception handling is started. 5. pc, ccr, and exr are saved to the stack area in interrupt exception handling. the pc value saved on the stack shows the address of the first instruction to be executed after returning from the interrupt service routine. 6. the t bit in exr is cleared to 0. as a result, the interrupt mask level is rewritten with the priority level of the accepted interrupt. if the accepted interrupt is nmi, the interrupt mask level is set to h'7. 7. a vector address is generated for the accepted interrupt, and execution of the interrupt service routine starts at the address indicated by the contents of that vector address.
80 yes program execution state interrupt generated? nmi? level 6 interrupt? mask level 5 or below? level 7 interrupt? mask level 6 or below? save pc, ccr, and exr clear t bit to 0 update mask level read vector address branch to interrupt service routine hold pending level 1 interrupt? mask level 0? yes yes no yes yes yes no yes yes no no no no no no figure 3.6 flowchart of procedure up to interrupt acceptance in interrupt control mode 2
81 3.5.4 interrupt exception handling sequence figure 3.7 shows the interrupt exception handling sequence. the example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory.
82 (14) (12) (10) (6) (4) (2) (1) (5) (7) (9) (13) interrupt service routine instruction prefetch internal operation vector fetch stack instruction prefetch internal operation interrupt acceptance interrupt level determination wait for end of instruction interrupt request signal internal address bus internal read signal internal write signal internal data bus (3) (1) instruction prefetch address (not executed; saved pc contents (return address)) (2), (4) instruction code (not executed) (3) instruction prefetch address (not executed) (5) sp 2 (7) sp 4 (6), (8) saved pc and saved ccr (9), (11) vector address (10), (12) interrupt service routine start address (vector address contents) (13) interrupt service routine start address ((13) = (10), (12)) (14) first instruction of interrupt service routine (8) (11) figure 3.7 interrupt exception handling
83 3.5.5 interrupt response times the h8s/2678 series is capable of fast word access to on-chip memory, and the program area is provided in on-chip rom and the stack area in on-chip ram, enabling high-speed processing. table 3.10 shows interrupt response times?he interval between generation of an interrupt request and execution of the first instruction in the interrupt service routine. the symbols used in table 3.10 are explained in table 3.11. table 3.10 interrupt response times advanced mode no. item intm1 = 0 intm1 = 1 1 interrupt priority determination * 1 33 2 number of wait states until executing instruction ends * 2 1 to 19 + 2 ? ? ? ? ? ? * 3 2 ? ? * 4 22 total (using on-chip memory) 12 to 32 13 to 33 notes: 1. two states in case of internal interrupt. 2. refers to mulxs and divxs instructions. 3. prefetch after interrupt acceptance and interrupt service routine prefetch. 4. internal processing after interrupt acceptance and internal processing after vector fetch. table 3.11 number of states in interrupt exception handling object of access external device 8-bit bus 16-bit bus symbol internal memory 2-state access 3-state access 2-state access 3-state access instruction fetch s i 1 4 6 + 2m 2 3 + m branch address read s j stack manipulation s k legend m: number of wait states in an external device access
84 3.6 usage notes 3.6.1 contention between interrupt generation and disabling when an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. in other words, when an interrupt enable bit is cleared to 0 by an instruction such as bclr or mov, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. however, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. the same also applies when an interrupt source flag is cleared to 0. figure 3.8 shows an example in which the tgiea bit in the tpu? tier0 register is cleared to 0. internal address bus internal write signal tgiea tgfa tgi0a interrupt signal tier0 write cycle by cpu tgi0a exception handling tier0 address figure 3.8 contention between interrupt generation and disabling the above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked.
85 3.6.2 instructions that disable interrupts instructions that disable interrupts are ldc, andc, orc, and xorc. after any of these instructions is executed, all interrupts except nmi are disabled and the next instruction is always executed. when the i bit is set by one of these instructions, the new value is valid two states after instruction execution is completed. 3.6.3 periods when interrupts are disabled there are periods during which interrupt acceptance by the interrupt controller is disabled. the interrupt controller disables interrupt acceptance for a 3-state period after the cpu has updated the mask level with an ldc, andc, orc, or xorc instruction. 3.6.4 interrupts during execution of eepmov instruction the eepmov.b instruction and eepmov.w instruction differ in their reaction to interrupt requests. with the eepmov.b instruction, an interrupt request (including nmi) issued during the transfer is not accepted until the transfer is completed. with the eepmov.w instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. the pc value saved on the stack in this case is the address of the next instruction. the following coding should be used to allow for interrupts generated during execution of an eepmov.w instruction. l1: eepmov.w mov.w r4,r4 bne l1 3.7 dtc and dmac activation by interrupt 3.7.1 overview the dtc and dmac can be activated by an interrupt. in this case, the following options are available. some models do not have an on-chip dmac; see the reference manual for the relevant model for details.
86 1. interrupt request to cpu 2. activation request to dtc 3. activation request to dmac 4. selection of a number of the above for details of interrupt requests that can be used to activate the dtc or dmac, see section 6, data transfer controller, and section 5, dma controller, in the h8s/2678 series hardware manual. 3.7.2 block diagram figure 3.9 shows a block diagram of the dtc, dmac, and interrupt controller. dmac selection circuit dtcer dtvecr control logic priority determination cpu dtc select signal irq interrupt on-chip supporting module clear signal interrupt controller i, i2 to i0 dtc activation request vector number cpu interrupt request vector number swdte clear signal clear signal interrupt source clear signal disable signal clear signal interrupt request figure 3.9 interrupt control for dtc and dmac
87 3.7.3 operation the interrupt controller has three main functions in dtc and dmac control. selection of interrupt source: with the dmac, the activation source is input directly to each channel. the activation source for each dmac channel is selected with bits dtf3 to dtf0 in dmacr. the selected activation source can be managed by the dmac or selected with the dta bit in dmabcr. when the dta bit is set to 1, the interrupt source constituting that dmac activation source does not function as a dtc activation source or cpu interrupt source. for interrupt sources other than interrupts managed by the dmac, it is possible to select dtc activation request or cpu interrupt request with the dtce bit of dtcera to dtcerh in the dtc. the disel bit in the dtc? mrb register can be used to specify clearing of the dtce bit to 0 and issuance of an interrupt request to the cpu after a dtc data transfer. when the dtc has performed the specified number of data transfers and the transfer counter value is 0, following the dtc data transfer the dtce bit is cleared to 0 and an interrupt request is sent to the cpu. determination of priority: the dtc activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. priorities are shown in table 3.12. with the dmac, the activation source is input directly to each channel. operation order: if the same interrupt is selected as a dtc activation source and a cpu interrupt source, the dtc data transfer is performed first, followed by cpu interrupt exception handling. if the same interrupt is selected as a dmac activation source and a dtc activation source or cpu interrupt source, operations are performed for them independently according to their respective operating statuses and bus mastership priorities. table 3.13 summarizes interrupt source selection and interrupt source clearance control according to the settings of the dta bit of dmabcr in the dmac, the dtce bit of dtcera to dtcerh in the dtc, and the disel bit of mrb in the dtc.
88 table 3.12 interrupt sources, dtc vector addresses, and corresponding dtce bits interrupt source origin of interrupt source vector number vector address advanced mode dtce * priority write to dtvecr software dtvecr h'0400+ (dtvecr[6:0]<<1) high irq0 external pin 16 h'0420 dtcea7 irq1 17 h'0422 dtcea6 irq2 18 h'0424 dtcea5 irq3 19 h'0426 dtcea4 irq4 20 h'0428 dtcea3 irq5 21 h'042a dtcea2 irq6 22 h'042c dtcea1 irq7 23 h'042e dtcea0 irq8 24 h'0430 dtceb7 irq9 25 h'0432 dtceb6 irq10 26 h'0434 dtceb5 irq11 27 h'0436 dtceb4 irq12 28 h'0438 dtceb3 irq13 29 h'043a dtceb2 irq14 30 h'043c dtceb1 irq15 31 h'043e dtceb0 adi (a/d conversion end) a/d 38 h'044c dtcec6 tgi0a (tgr0a compare match/input capture) tpu channel 0 40 h'0450 dtcec5 tgi0b (tgr0b compare match/input capture) 41 h'0452 dtcec4 tgi0c (tgr0c compare match/input capture) 42 h'0454 dtcec3 tgi0d (tgr0d compare match/input capture) 43 h'0456 dtcec2 tgi1a (tgr1a compare match/input capture) tpu channel 1 48 h'0460 dtcec1 tgi1b (tgr1b compare match/input capture) 49 h'0462 dtcec0 tgi2a (tgr2a compare match/input capture) tpu channel 2 52 h'0468 dtced7 tgi2b (tgr2b compare match/input capture) 53 h'046a dtced6 low
89 interrupt source origin of interrupt source vector number vector address advanced mode dtce * priority tgi3a (tgr3a compare match/input capture) tpu channel 3 56 h'0470 dtced5 high tgi3b (tgr3b compare match/input capture) 57 h'0472 dtced4 tgi3c (tgr3c compare match/input capture) 58 h'0474 dtced3 tgi3d (tgr3d compare match/input capture) 59 h'0476 dtced2 tgi4a (tgr4a compare match/input capture) tpu channel 4 64 h'0480 dtced1 tgi4b (tgr4b compare match/input capture) 65 h'0482 dtced0 tgi5a (tgr5a compare match/input capture) tpu channel 5 68 h'0488 dtcee7 tgi5b (tgr5b compare match/input capture) 69 h'048a dtcee6 cmi0a (compare match a) 8-bit timer channel 0 72 h'0490 dtcee3 cmi0b (compare match b) 73 h'0492 dtcee2 cmi1a (compare match a) 8-bit timer channel 1 76 h'0498 dtcee1 cmi1b (compare match b) 77 h'049a dtcee0 dmtend0a (channel 0/channel 0a transfer end) dmac 80 h'04a0 dtcef7 dmtend0b (channel 0b transfer end) 81 h'04a2 dtcef6 dmtend1a (channel 1/channel 1a transfer end) 82 h'04a4 dtcef5 dmtend1b (channel 1b transfer end) 83 h'04a6 dtcef4 rxi0 (receive completed 0) sci channel 0 89 h'04b2 dtcef3 txi0 (transmit data empty 0) 90 h'04b4 dtcef2 rxi1 (receive completed 1) sci channel 1 93 h'04ba dtcef1 txi1 (transmit data empty 1) 94 h'04bc dtcef0 rxi2 (receive completed 2) sci channel 2 97 h'04c2 dtceg7 txi2 (transmit data empty 2) 98 h'04c4 dtceg6 low note: * dtce bits with no corresponding interrupt are reserved, and should be written with 0. when clearing the software standby state or all-module-clocks-stop mode with an interrupt, write 0 to the corresponding dtce bit.
90 table 3.13 interrupt source selection and clearing control settings dmac dtc interrupt source selection/clearing control dta dtce disel dmac dtc cpu 00 * x 10 x 1 1 ** xx legend : the relevant interrupt is used. interrupt source clearing is performed. (the cpu should clear the source flag in the interrupt service routine.) : the relevant interrupt is used. the interrupt source is not cleared. x : the relevant bit cannot be used. * : don t care usage note: sci and a/d converter interrupt sources are cleared when the dmac or dtc reads or writes to the prescribed register, and are not dependent on the dta and disel bits.
91 section 4 bus controller 4.1 overview the h8s/2678 series has an on-chip bus controller (bsc) that manages the external address space divided into eight areas. the bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories and external i/o devices to be connected easily. the bus controller also has a bus arbitration function, and controls the operation of the internal bus masters?he cpu, dma controller (dmac), data transfer controller (dtc), and external bus transfer dmac (exdmac). 4.1.1 features the features of the bus controller are listed below. ? manages external address space in area units ? manages the external space as eight areas of 2 mbytes ? bus specifications can be set independently for each area ? 8-bit access or 16-bit access can be selected for each area ? dram and burst rom interfaces can be set ? basic bus interface ? chip select signals ( cs0 to cs7 ) can be output for areas 0 to 7 ? 2-state access or 3-state access can be selected for each area ? program wait states can be inserted for each area ? cs assertion period extension states can be inserted for each area ? dram interface ? dram interface can be set for areas 2 to 5 ? row address/column address multiplexed output (8/9/10/11 bits) ? 2-cas access method for byte control ? burst operation using fast page mode ? t p cycle insertion to secure ras precharging time ? selection of cas-before-ras (cbr) refreshing or self-refreshing ? oe signal can be output ? continuous dram space can be designated for areas 2 to 5 ? burst rom interface ? burst rom interface can be set for area 0 and area 1 ? area 0 and area 1 burst rom interfaces can be set independently
92 ? idle cycle insertion ? an idle cycle can be inserted in case of external read cycles in different areas ? an idle cycle can be inserted in case of an external write cycle immediately after an external read cycle ? write buffer function ? external write cycle and internal access can be executed in parallel ? dmac single address mode and internal access can be executed in parallel ? bus arbitration function ? includes a bus arbiter that arbitrates bus mastership between the cpu, dmac, dtc, and exdmac ? other features ? refresh counter (refresh timer) can be used as an interval timer ? external bus release function ? exdmac external bus transfer and internal access can be executed in parallel
93 4.1.2 block diagram area decoder internal address bus exdmac address bus cs7 to cs0 wait breq back breqo external bus control signals internal bus control signals internal data bus control registers address selector external bus arbiter external bus controller internal bus arbiter internal bus controller internal bus master bus request signal exdmac bus request signal internal bus master bus acknowledge signal exdmac bus acknowledge signal cpu bus request signal dtc bus request signal dmac bus request signal cpu bus acknowledge signal dtc bus acknowledge signal dmac bus acknowledge signal abwcr astcr wtcrah wtcral wtcrbh wtcrbl rdncr dramcrh dramcrl draccr refcrh refcrl rtcnt rtcor csacrh csacrl bromcrh bromcrl bcrl bcrh figure 4.1 block diagram of bus controller
94 4.1.3 pin configuration table 4.1 summarizes the pins of the bus controller. table 4.1 bus controller pins name abbre- viation i/o function address strobe as output strobe signal indicating that address output on address bus is enabled during access to basic bus interface space. read rd output strobe signal indicating that basic bus interface space is being read. high write/write enable hwr output strobe signal indicating that basic bus interface space is being written to, and upper half (d15 to d8) of data bus is enabled. dram interface space write enable signal. low write lwr output strobe signal indicating that basic bus interface space is being written to, and lower half (d7 to d0) of data bus is enabled. chip select 0 cs0 output strobe signal indicating that area 0 is selected. chip select 1 cs1 output strobe signal indicating that area 1 is selected. chip select 2/row address strobe 2 cs2 output strobe signal indicating that area 2 is selected. dram row address strobe signal when area 2 is dram interface space or areas 2 to 5 are continuous dram interface space. chip select 3/row address strobe 3 cs3 output strobe signal indicating that area 3 is selected. dram row address strobe signal when area 3 is dram interface space. chip select 4/row address strobe 4 cs4 output strobe signal indicating that area 4 is selected. dram row address strobe signal when area 4 is dram interface space.
95 name abbre- viation i/o function chip select 5/row address strobe 5 cs5 output strobe signal indicating that area 5 is selected. dram row address strobe signal when area 5 is dram interface space. chip select 6 cs6 output strobe signal indicating that area 6 is selected. chip select 7 cs7 output strobe signal indicating that area 7 is selected. upper column address strobe ucas output 16-bit dram interface space upper column address strobe signal. 8-bit dram interface space column address strobe signal. lower column address strobe lcas output 16-bit dram interface space lower column address strobe signal. output enable oe output dram interface space output enable signal. wait wait input wait request signal when accessing external space. bus request breq input request signal for release of bus to external device. bus request acknowledge back output acknowledge signal indicating that bus has been released. bus request output breqo output external bus request signal used when internal bus master accesses external space when external bus is released. data transfer acknowledge 1 (dmac) dack1 output data transfer acknowledge signal for single address transfer by dmac channel 1. data transfer acknowledge 0 (dmac) dack0 output data transfer acknowledge signal for single address transfer by dmac channel 0. data transfer acknowledge 3 (exdmac) edack3 output data transfer acknowledge signal for single address transfer by exdmac channel 3. data transfer acknowledge 2 (exdmac) edack2 output data transfer acknowledge signal for single address transfer by exdmac channel 2. data transfer acknowledge 1 (exdmac) edack1 output data transfer acknowledge signal for single address transfer by exdmac channel 1. data transfer acknowledge 0 (exdmac) edack0 output data transfer acknowledge signal for single address transfer by exdmac channel 0.
96 4.1.4 register configuration table 4.2 summarizes the registers of the bus controller. table 4.2 bus controller registers initial value register size name abbreviation r/w reset address * 1 (bits) bus width control register abwcr r/w h'ff/h'00 * 2 h'fec0 8 access state control register astcr r/w h'ff h'fec1 8 wait control register a wtcra r/w h'7777 h'fec2 16 wait control register b wtcrb r/w h'7777 h'fec4 16 read strobe timing control register rdncr r/w h'00 h'fec6 8 chip select assertion period control csacrh r/w h'00 h'fec8 8 registers csacrl r/w h'00 h'fec9 8 burst rom interface control registers bromcrh r/w h'00 h'feca 8 bromcrl r/w h'00 h'fecb 8 bus control register bcr r/w h'1c00 h'fecc 16 dram control register dramcr r/w h'0000 h'fed0 16 dram access control register draccr r/w h'00 h'fed2 8 refresh control register refcr r/w h'0000 h'fed4 16 refresh timer counter rtcnt r/w h'00 h'fed6 8 refresh time constant register rtcor r/w h'ff h'fed7 8 notes: 1. lower 16 bits of the address. 2. determined by the mcu operating mode.
97 4.2 register descriptions 4.2.1 bus width control register (abwcr) bit 76543210 abw7 abw6 abw5 abw4 abw3 abw2 abw1 abw0 modes 2, 4, 6 initial value 11111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w modes 1, 5, 7 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w abwcr is an 8-bit readable/writable register that designates each area as either 8-bit access space or 16-bit access space. abwcr sets the data bus width for the external memory space. the bus width for on-chip memory and internal i/o registers is fixed regardless of the settings in abwcr. after a reset and in hardware standby mode, abwcr is initialized to h'ff in modes 2, 4, and 6, and to h'00 in modes 1, 5, and 7. it is not initialized in software standby mode. bits 7 to 0?rea 7 to 0 bus width control (abw7 to abw0): these bits select whether the corresponding area is to be designated as 8-bit access space or 16-bit access space. bit n abwn description 0 area n is designated as 16-bit access space 1 area n is designated as 8-bit access space (n = 7 to 0) 4.2.2 access state control register (astcr) bit 76543210 ast7 ast6 ast5 ast4 ast3 ast2 ast1 ast0 initial value 11111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w astcr is an 8-bit readable/writable register that designates each area as either 2-state access space or 3-state access space.
98 astcr sets the number of access states for the external memory space. the number of access states for on-chip memory and internal i/o registers is fixed regardless of the settings in astcr. astcr is initialized to h'ff by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 to 0?rea 7 to 0 access state control (ast7 to ast0): these bits select whether the corresponding area is to be designated as 2-state access space or 3-state access space. wait state insertion is enabled or disabled at the same time. bit n astn description 0 area n is designated as 2-state access space wait state insertion in area n external space access is disabled 1 area n is designated as 3-state access space (initial value) wait state insertion in area n external space access is enabled (n = 7 to 0) 4.2.3 wait control registers a and b (wtcra, wtcrb) wtcra and wtcrb are 16-bit readable/writable registers that select the number of program wait states for each area. program waits are not inserted in on-chip memory or internal i/o register access. wtcra and wtcrb are initialized to h'7777 by a reset and in hardware standby mode. they are not initialized in software standby mode. wtcra bit 15 14 13 12 11 10 9 8 w72 w71 w70 w62 w61 w60 initial value 01110111 read/write r r/w r/w r/w r r/w r/w r/w bit 76543210 w52 w51 w50 w42 w41 w40 initial value 01110111 read/write r r/w r/w r/w r r/w r/w r/w
99 wtcrb bit 15 14 13 12 11 10 9 8 w32 w31 w30 w22 w21 w20 initial value 01110111 read/write r r/w r/w r/w r r/w r/w r/w bit 76543210 w12 w11 w10 w02 w01 w00 initial value 01110111 read/write r r/w r/w r/w r r/w r/w r/w bits 15, 11, 7, and 3?eserved: these bits are always read as 0 and cannot be modified. bits 14 to 12, 10 to 8, 6 to 4, 2 to 0?ait control (wn2, wn1, wn0): these bits select the number of program wait states for areas designated as 3-state access space in astcr. wn2 wn1 wn0 description 0 0 0 program wait not inserted in area n external access 1 1 program wait state inserted in area n external access 1 0 2 program wait states inserted in area n external access 1 3 program wait states inserted in area n external access 1004 program wait states inserted in area n external access 1 5 program wait states inserted in area n external access 1 0 6 program wait states inserted in area n external access 1 7 program wait states inserted in area n external access (n = 7 to 0) 4.2.4 read strobe timing control register (rdncr) bit 76543210 rdn7 rdn6 rdn5 rdn4 rdn3 rdn2 rdn1 rdn0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w rdncr is an 8-bit readable/writable register that selects the read strobe ( rd ) negation timing when an area is designated as basic bus interface space.
100 rdncr is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 to 0?ead strobe timing control (rdnn): as shown in figure 4.2, the read strobe for an area for which the rdnn bit is set to 1 is negated one half-state earlier than that for an area for which the rdnn bit is cleared to 0. the read data setup and hold time specifications are also one half-state earlier. the read strobe is negated one half-state earlier regardless of 2-state or 3-state access designation, or the number of program waits. bit 7 to 0 rdnn description 0 in an area n read access, the rd strobe is negated at the end of the read cycle (initial value) 1 in an area n read access, the rd strobe is negated one half-state before the end of the read cycle (n = 7 to 0) bus cycle t 1 t 2 rd rd figure 4.2 read strobe negation timing (example of 3-state access space)
101 4.2.5 cs assertion period control registers (csacrh, csacrl) csacrh bit 76543210 csxh7 csxh6 csxh5 csxh4 csxh3 csxh2 csxh1 csxh0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w csacrl bit 76543210 csxt7 csxt6 csxt5 csxt4 csxt3 csxt2 csxt1 csxt0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w csacrh and csacrl are 8-bit readable/writable registers that specify whether or not the assertion period of the basic bus interface chip select signals ( csn ) and address signals is to be extended. extending the assertion period of the csn and address signals allows flexible interfacing to external i/o devices. csacrh and csacrl are initialized to h'0000 by a reset and in hardware standby mode. they are not initialized in software standby mode.
102 csacrh bits 7 to 0 cs and address signal assertion period control 1 (csxh7 to csxh0): these bits specify whether or not the t h cycle shown in figure 4.3 is to be inserted. when an area for which the csxhn bit is set to 1 is accessed, a t h state, in which only the csn and address signals are asserted, is inserted before the normal access cycle. a one-state t h cycle is inserted regardless of 2-state or 3-state access designation, or the number of program waits. bit n csxhn description 0 in area n basic bus interface access, the csn csn csacrl bits 7 to 0 cs and address signal assertion period control 2 (csxt7 to csxt0): these bits specify whether or not the t t cycle shown in figure 4.3 is to be inserted. when an area for which the csxtn bit is set to 1 is accessed, a t t state, in which only the csn and address signals are asserted, is inserted after the normal access cycle. a one-state t t cycle is inserted regardless of 2-state or 3-state access designation, or the number of program waits. bit n csxtn description 0 in area n basic bus interface access, the csn csn
103 t h address t 1 t 2 t 3 t t bus cycle data hwr lwr rd cs figure 4.3 cs and address assertion period extension (example of 3-state access space and rdwn = 0) 4.2.6 area 0 burst rom i/f control register (bromcrh) area 1 burst rom i/f control register (bromcrl) bromcrh bit 76543210 bsrm0 bsts02 bsts01 bsts00 bswd01 bswd00 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w bromcrl bit 76543210 bsrm1 bsts12 bsts11 bsts10 bswd11 bswd10 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w
104 bromcrh and bromcrl are 8-bit readable/writable registers used to make burst rom interface settings. area 1 and area 0 burst rom interface settings can be made independently in bromcrh and bromcrl, respectively. bromcrh and bromcrl are initialized to h'0000 by a reset and in hardware standby mode. they are not initialized in software standby mode. bit 7?urst rom interface select (bsrmn): selects the burst rom interface for area 0 or area 1. bit 7 bsrmn description 0 area n is basic bus interface space (initial value) 1 area n is burst rom interface space (n = 1 or 0) bits 6 to 4?urst cycle select (bstsn2, bstsn1, bstsn0): these bits select the number of burst cycle states. bit 6 bstsn2 bit 5 bstsn1 bit 4 bstsn0 description 0 0 0 area n burst cycle comprises 1 state (initial value) 1 area n burst cycle comprises 2 states 1 0 area n burst cycle comprises 3 states 1 area n burst cycle comprises 4 states 1 0 0 area n burst cycle comprises 5 states 1 area n burst cycle comprises 6 states 1 0 area n burst cycle comprises 7 states 1 area n burst cycle comprises 8 states (n = 1 or 0) bits 3 and 2?eserved: these are readable/writable bits, but the write value should always be 0. bits 1 and 0?urst word length select (bswdn1, bswdn0): these bits select the number of words that can be burst-accessed on the burst rom interface.
105 bit 1 bswdn1 bit 0 bswdn0 description 0 0 maximum 4 words in area n burst access (initial value) 1 maximum 8 words in area n burst access 1 0 maximum 16 words in area n burst access 1 maximum 32 words in area n burst access (n = 1 or 0) 4.2.7 bus control register (bcr) bit 15 14 13 12 11 10 9 8 brle breqoe idlc icis1 icis0 wdbe waite initial value 00011100 read/write r/w r/w r/w r/w r/w r/w r/w r/w bit 76543210 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w bcr is a 16-bit readable/writable register used for idle cycle settings, selection of the external bus released state protocol, enabling or disabling of the write data buffer function, and enabling or disabling of wait pin input. bcr is initialized to h'1c00 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 15?xternal bus release enable (brle): enables or disables external bus release by means of the breq pin. bit 15 brle description 0 external bus release disabled breq back breqo bit 14 breqo pin enable (breqoe): selects whether or not to output a signal that requests the external bus master to drop the bus request signal ( breq ) in the external bus released state,
106 when an internal bus master performs an external space access, or when a refresh request is generated. bit 14 breqoe description 0 breqo breqo breqo bit 13?eserved: this is a readable/writable bit, but the write value should always be 0. bit 12?dle cycle state number select (idlc): selects the number of states in the idle cycle set by icis1 and icis0. bit 12 idlc description 0 idle cycle comprises 1 state 1 idle cycle comprises 2 states (initial value) bit 11?dle cycle insert 1 (icis1): when consecutive external read cycles are performed in different areas, an idle cycle can be inserted between the bus cycles. when this bit is set to 1, an idle cycle is inserted in the case of consecutive external read cycles in different areas. bit 11 icis1 description 0 idle cycle not inserted in case of consecutive external read cycles in different areas 1 idle cycle inserted in case of consecutive external read cycles in different areas (initial value) bit 10?dle cycle insert 0 (icis0): when an external read cycle and external write cycle are performed consecutively, an idle cycle can be inserted between the bus cycles. when this bit is set to 1, an idle cycle is inserted when an external read cycle and external write cycle are performed consecutively. bit 10 icis0 description 0 idle cycle not inserted when external read cycle and external write cycle are performed consecutively 1 idle cycle inserted when external read cycle and external write cycle are performed consecutively (initial value)
107 bit 9?rite data buffer enable (wdbe): selects whether or not the write data buffer function is used for an external write cycle or dmac single address transfer cycle. bit 9 wdbe description 0 write data buffer function not used (initial value) 1 write data buffer function used bit 8 wait pin enable (waite): selects enabling or disabling of wait input by the wait pin. bit 8 waite description 0 wait input by wait wait wait bits 7 to 0?eserved: these are readable/writable bits, but the write value should always be 0. 4.2.8 dram control register (dramcr) bit 15 14 13 12 11 10 9 8 oee rast cast rmts2 rmts1 rmts0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w bit 76543210 be rcdm dds edds mxc2 mxc1 mxc0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w dramcr is a 16-bit readable/writable register used to make dram interface settings. dramcr is initialized to h'0000 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 15 oe output enable (oee): enables or disables output from the oe pin of the oe signal used when edo page mode dram is connected. the oe signal is common to all areas designated as dram space.
108 bit 15 oee description 0 oe oe oe bit 14 ras assertion timing select (rast): selects whether, in dram access, the ras signal is asserted from the start of the t r cycle (rising edge of ? or from the falling edge of ? figure 4.4 shows the relationship between the rast bit setting and the ras assertion timing. the setting of this bit applies to all areas designated as dram space. bit 14 rast description 0 ras falling edge in t r cycle (initial value) 1 ras ras ras ucas lcas figure 4.4 ras signal assertion timing (2-state column address output cycle, full access) bit 13?eserved: this is a readable/writable bit, but the write value should always be 0.
109 bit 12?olumn address output cycle number select (cast): selects whether the column address output cycle in dram access comprises 3 states or 2 states. the setting of this bit applies to all areas designated as dram space. bit 12 cast description 0 column address output cycle comprises 2 states (initial value) 1 column address output cycle comprises 3 states bit 11?eserved: this is a readable/writable bit, but the write value should always be 0. bits 10 to 8?ram space select (rmts2 to rmts0): these bits designate dram space for areas 2 to 5. when continuous dram space is set, it is possible to connect large-capacity dram exceeding 2 mbytes per area. in this case, the ras signal is output from the ras2 pin. bit 10 bit 9 bit 8 description rmts2 rmts 1 rmts 0 area 5 area 4 area 3 area 2 0 0 0 normal space normal space normal space normal space 1 normal space normal space normal space dram space 1 0 normal space normal space dram space dram space 1 dram space dram space dram space dram space 10 * reserved reserved reserved reserved 10 (setting prohibited) (setting prohibited) (setting prohibited) (setting prohibited) 1 continuous dram space continuous dram space continuous dram space continuous dram space * : don t care bit 7?urst access enable (be): selects enabling or disabling of burst access to areas designated as dram space. dram space burst access is performed in fast page mode. when using edo page mode dram, the oe signal must be connected. bit 7 be description 0 full access always used for dram space access (initial value) 1 dram space access performed in fast page mode
110 bit 6 ras down mode (rcdm): when access to dram space is interrupted by an access to normal bus space, an access to an internal i/o register, etc., this bit selects whether the ras signal is held low while waiting for the next dram access ( ras down mode), or is driven high again ( ras up mode). the setting of this bit is valid only when the be bit is set to 1. if this bit is cleared to 0 when set to 1 in the ras down state, the ras down state is cleared at that point, and ras goes high. bit 6 rcdm description 0 ras ras bit 5?mac single address transfer option (dds): specifies whether full access is always performed or burst access is enabled when dmac single address transfer is performed on the dram interface. when the be bit is cleared to 0 in dramcr, disabling dram burst access, dmac single address transfer is performed in full access mode regardless of the setting of the dds bit. this bit has no effect on other bus master external accesses or dmac dual address transfers. bit 5 dds description 0 full access is always executed when dmac single address transfer is performed in dram space (initial value) 1 burst access is possible when dmac single address transfer is performed in dram space bit 4?xdmac single address transfer option (edds): specifies whether full access is always performed or burst access is enabled when exdmac single address transfer is performed on the dram interface. when the be bit is cleared to 0 in dramcr, disabling dram burst access, exdmac single address transfer is performed in full access mode regardless of the setting of the edds bit. this bit has no effect on other bus master external accesses or exdmac dual address transfers.
111 bit 4 edds description 0 full access is always executed when exdmac single address transfer is performed in dram space (initial value) 1 burst access is possible when exdmac single address transfer is performed in dram space bit 3?eserved: this is a readable/writable bit, but the write value should always be 0. bits 2 to 0?ddress multiplex select (mxc2 to mxc0): these bits select the size of the shift toward the lower half of the row address in row address/column address multiplexing. in burst operation on the dram interface, these bits also select the row address bits to be used for comparison. bit 2 mxc2 bit 1 mxc1 bit 0 mxc0 description 0 0 0 8-bit shift (initial value) ? ? ? ? ? ? ? ? reserved (setting prohibited)
112 4.2.9 dram access control register (draccr) bit 76543210 drmi tpc1 tpc0 rcd1 rcd0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w draccr is an 8-bit readable/writable register used to set the dram interface bus specifications. draccr is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7?dle cycle insertion (drmi): selects whether or not an idle cycle is inserted when a normal access cycle follows a dram read cycle. bit 7 drmi description 0 idle cycle not inserted after dram space access (initial value) 1 idle cycle inserted after dram space access idle cycle insertion conditions, setting of number of states, etc., comply with settings of bits icis1, icis0, and idlc in bcr register bit 6?eserved: this is a readable/writable bit, but the write value should always be 0. bits 5 and 4?recharge state control (tpc1, tpc0): these bits select the number of states in the ras precharge cycle in normal access and refreshing. from 1 to 4 states can be set for the precharge cycle. bit 5 tpc1 bit 4 tpc0 description 00 ras ras ras ras bits 3 and 2?eserved: these are readable/writable bits, but the write value should always be 0. bits 1 and 0?as-cas wait control (rcd1, rcd0): these bits select whether or not a wait cycle is to be inserted between the ras assert cycle and cas assert cycle. a 1- to 4-state wait cycle can be inserted.
113 bit 1 rcd1 bit 0 rcd0 description 0 0 wait cycle not inserted between ras cas ras cas ras cas ras cas 4.2.10 refresh control register (refcr) bit 15 14 13 12 11 10 9 8 cmf cmie rcw1 rcw0 rtck2 rtck1 rtck0 initial value 00000000 read/write r/w * r/w r/w r/w r/w r/w r/w r/w bit 76543210 rfshe cbrm rlw1 rlw0 slfrf tpcs2 tpcs1 tpcs0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w note: * only 0 can be written, to clear the flag. refcr is a 16-bit readable/writable register that specifies dram interface refresh control. refcr is initialized to h'0000 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 15?ompare match flag (cmf): status flag that indicates a match between the values of the refresh counter (rtcnt) and the refresh time constant register (rtcor).
114 bit 15 cmf description 0 [clearing conditions] ? ? bit 14?ompare match interrupt enable (cmie): enables or disables interrupt requests (cmi) by the cmf flag when the cmf flag is set to 1. this bit is valid only when refresh control is not performed (when the rfshe bit is cleared to 0). when the rfshe bit is set to 1 and refresh control is performed, the cmie bit is always cleared to 0 and cannot be modified. bit 14 cmie description 0 interrupt request by cmf flag disabled (initial value) 1 interrupt request by cmf flag enabled bits 13 and 12 cas - ras wait control (rcw1, rcw0): these bits select whether or not a wait cycle is to be inserted between the cas assert cycle and ras assert cycle in a dram refresh cycle. a 1- to 3-state wait cycle can be inserted. bit 13 rcw1 bit 12 rcw0 description 0 0 wait state not inserted between cas ras cas ras cas ras cas ras bit 11?eserved: this is a readable/writable bit, but the write value should always be 0. bits 10 to 8?efresh counter clock select (rtck2 to rtck0): these bits select the clock to be used to increment the refresh counter from among seven internal clocks obtained by dividing the system clock (?. when the input clock is selected with bits rtck2 to rtck0, the refresh counter begins counting up.
115 bit 10 rtck2 bit 9 rtck1 bit 8 rtck0 description 0 0 0 count operation halted (initial value) 1 count on /2 1 0 count on /8 1 count on /32 1 0 0 count on /128 1 count on /512 1 0 count on /2048 1 count on /4096 bit 7?efresh control (rfshe): selects whether or not refresh control is performed. when refresh control is not performed, the refresh timer can be used as an interval timer. bit 7 rfshe description 0 refresh control is not performed 1 refresh control is performed (initial value) bit 6?br refresh mode (cbrm): allows selection of cbr refreshing performed in parallel with other external accesses, or execution of cbr refreshing alone. bit 6 cbrm description 0 external access during cas-before-ras refreshing is enabled (initial value) 1 external access during cas-before-ras refreshing is disabled bits 5 and 4?efresh cycle wait control (rlw1, rlw0): these bits select the number of wait states to be inserted in a dram interface cas-before-ras refresh cycle. this setting applies to all areas designated as dram space. bit 5 rlw1 bit 4 rlw0 description 0 0 no wait state inserted in cbr refresh (initial value) 1 1 wait state inserted in cbr refresh 1 0 2 wait states inserted in cbr refresh 1 3 wait states inserted in cbr refresh
116 bit 3?elf-refresh enable (slfrf): if this bit is set to 1, dram self-refresh mode is selected when a transition is made to the software standby state. this bit is valid when the rfshe bit is set to 1, enabling refresh operations. it is cleared after recovery from software standby mode. bit 3 slfrf description 0 self-refreshing is disabled in software standby mode (initial value) 1 self-refreshing is enabled in software standby mode bits 2 to 0?elf-refresh precharge cycle control (tpcs2 to tpcs0): these bits select the number of states in the precharge cycle immediately after self-refreshing. the number of states in the precharge cycle immediately after self-refreshing are added to the number of states set by bits tpc1 and tpc0 in the draccr register. bit 2 tpcs2 bit 1 tpcs1 bit 0 tpcs0 description 000 ras ras ras ras ras ras ras ras
117 4.2.11 refresh timer counter (rtcnt) bit 76543210 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w rtcnt is an 8-bit readable/writable up-counter. rtcnt counts up using the internal clock selected by bits rtck2 to rtck0 in refcr. when rtcnt matches rtcor (compare match), the cmf flag in refcr is set to 1 and rtcnt is cleared to h'00. if the rfshe bit in refcr is set to 1 at this time, a refresh cycle is started. if the rfshe bit is cleared to 0 and the cmie bit in refcr is set to 1, a compare match interrupt (cmi) is generated. rtcnt is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. 4.2.12 refresh time control register (rtcor) bit 76543210 initial value 11111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w rtcor is an 8-bit readable/writable register that sets the period for compare match operations with rtcnt. the values of rtcor and rtcnt are constantly compared, and if they match, the cmf flag in refcr is set to 1 and rtcnt is cleared to h'00. rtcor is initialized to h'ff by a reset and in hardware standby mode. it is not initialized in software standby mode.
118 4.3 overview of bus control 4.3.1 area division the bus controller divides the 16-mbyte address space into eight areas, 0 to 7, in 2-mbyte units, and performs bus control for external space in area units. figure 4.5 shows an outline of the memory map. chip select signals ( cs0 to cs7 ) can be output for each area. area 0 (2 mbytes) h'000000 h'ffffff h'1fffff h'200000 area 1 (2 mbytes) h'3fffff h'400000 area 2 (2 mbytes) h'5fffff h'600000 area 3 (2 mbytes) h'7fffff h'800000 area 4 (2 mbytes) h'9fffff h'a00000 area 5 (2 mbytes) h'bfffff h'c00000 area 6 (2 mbytes) h'dfffff h'e00000 area 7 (2 mbytes) advanced mode figure 4.5 area divisions
119 4.3.2 bus specifications the external space bus specifications consist of five elements: (1) bus width, (2) number of access states, (3) number of program wait states, (4) read strobe timing, and (5) chip select ( cs ) assertion period extension states. the bus width and number of access states for on-chip memory and internal i/o registers are fixed, and are not affected by the bus controller. bus width: a bus width of 8 or 16 bits can be selected with abwcr. an area for which an 8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a16-bit access space. if all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-bit access, 16-bit bus mode is always set. number of access states: two or three access states can be selected with astcr. an area for which 2-state access is selected functions as a 2-state access space, and an area for which 3-state access is selected functions as a 3-state access space. with the dram interface and burst rom interface, the number of access states may be determined without regard to astcr. when 2-state access space is designated, wait insertion is disabled. when 3-state access space is designated, it is possible to insert program waits by means of the wtcra and wtcrb registers, and external waits by means of of the wait pin. number of program wait states: when 3-state access space is designated by astcr, the number of program wait states to be inserted automatically is selected with wtcra and wtcrb. from 0 to 7 program wait states can be selected. table 4.3 shows the bus specifications (bus width, access states, and program wait states) for each basic bus interface area.
120 table 4.3 bus specifications for each area (basic bus interface) abwcr astcr wtcra, wtcrb bus specifications (basic bus interface) abwn astn wn2 wn1 wn0 bus width access states program wait states 00 16 2 0 1 000 3 0 11 10 2 13 100 4 15 10 6 17 10 820 1 000 3 0 11 10 2 13 100 4 15 10 6 17 note: n = 0 to 7 read strobe timing: a setting can be made in rdncr to select either of two timings for the read strobe ( rd ) used in the basic bus interface space. chip select ( cs ) assertion period extension states: some external i/o devices require a setup time and hold time between address and cs signals and strobe signals such as rd , hwr , and lwr . settings can be made in the csacr registers to insert states in which only the cs , as , and address signals are asserted before and after a basic bus space access cycle. 4.3.3 memory interfaces the memory interfaces of the h8s/2678 series comprise a basic bus interface that allows direct connection of rom, sram, and so on; a dram interface that allows direct connection of dram; and a burst rom interface that allows direct connection of burst rom. the interface can be selected independently for each area.
121 an area for which the basic bus interface is designated functions as normal space, an area for which the dram interface is designated functions as dram space, and an area for which the burst rom interface is designated functions as burst rom space. the initial state of each area is basic bus interface, 3-state access space. the initial bus width is selected according to the operating mode. the bus specifications described here cover basic items only, and the sections on each memory interface (4.4, 4.5, and 4.6) should be referred to for further details. area 0: area 0 includes on-chip rom*, and in expanded mode with on-chip rom disabled, all of area 0 is external space. in expanded mode with on-chip rom enabled, the space excluding on- chip rom* is external space. when area 0 external space is accessed, the cs0 signal can be output. either basic bus interface or burst rom interface can be selected for area 0. note: * applies only to versions with rom. area 1: in externally expanded mode, all of area 1 is external space. when area 1 external space is accessed, the cs1 signal can be output. either basic bus interface or burst rom interface can be selected for area 1. areas 2 to 5: in externally expanded mode, areas 2 to 5 are all external space. when area 2 to 5 external space is accessed, signals cs2 to cs5 can be output. basic bus interface or dram interface can be selected for areas 2 to 5. with the dram interface, signals cs2 to cs5 are used as ras signals. if areas 2 to 5 are designated as continuous dram space, large-capacity (e.g. 64-mbit) dram can be connected. in this case, the cs2 signal is used as the ras signal for the continuous dram space. area 6: in externally expanded mode, all of area 6 is external space. when area 6 external space is accessed, the cs6 signal can be output. only the basic bus interface can be used for area 6. area 7: area 7 includes the on-chip ram and internal/o registers. in externally expanded mode, the space excluding the on-chip ram and internal i/o registers is external space. the on-chip ram is enabled when the rame bit is set to 1 in the system control register (syscr); when the rame bit is cleared to 0, the on-chip ram is disabled and the corresponding addresses are in external space.
122 when area 7 external space is accessed, the cs7 signal can be output. only the basic bus interface can be used for the area 7 memory interface. 4.3.4 chip select signals the chip can output chip select signals ( cs0 to cs7 ) for areas 0 to 7, the signal being driven low when the corresponding external space area is accessed. figure 4.6 shows an example of csn (n = 0 to 7) output timing. enabling or disabling of csn signal output is performed by setting the data direction register (ddr) bit for the port corresponding to the particular csn pin. in expanded mode with on-chip rom disabled, the cs0 pin is placed in the output state after a reset. pins cs1 to cs7 are placed in the input state after a reset and so the corresponding ddr bits should be set to 1 when outputting signals cs1 to cs7 . in expanded mode with on-chip rom enabled, pins cs0 to cs7 are all placed in the input state after a reset and so the corresponding ddr bits should be set to 1 when outputting signals cs0 to cs7 . for details see section 5, i/o ports. when areas 2 to 5 are designated as dram space, outputs cs2 to cs5 are used as ras signals. bus cycle t 1 t 2 t 3 area n external address address bus csn figure 4.6 csn signal output timing (n = 0 to 7)
123 4.4 basic bus interface 4.4.1 overview the basic bus interface enables direct connection of rom, sram, and so on. the bus specifications can be selected with abwcr, astcr, wtcra, wtcrb, rdncr, and csacr. for details see table 4.3. 4.4.2 data size and data alignment data sizes for the cpu and other internal bus masters are byte, word, and longword. the bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (d15 to d8) or lower data bus (d7 to d0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data size. 8-bit access space: figure 4.7 illustrates data alignment control for the 8-bit access space. with the 8-bit access space, the upper data bus (d15 to d8) is always used for accesses. the amount of data that can be accessed at one time is one byte: a word access is performed as two byte accesses, and a longword access, as four byte accesses. d15 d8 d7 d0 upper data bus lower data bus byte size word size 1st bus cycle 2nd bus cycle longword size 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle figure 4.7 access sizes and data alignment control (8-bit access space)
124 16-bit access space: figure 4.8 illustrates data alignment control for the 16-bit access space. with the 16-bit access space, the upper data bus (d15 to d8) and lower data bus (d7 to d0) are used for accesses. the amount of data that can be accessed at one time is one byte or one word, and a longword access is executed as two word accesses. in byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. the upper data bus is used for an even address, and the lower data bus for an odd address. d15 d8 d7 d0 upper data bus lower data bus byte size word size 1st bus cycle 2nd bus cycle longword size even address byte size odd address figure 4.8 access sizes and data alignment control (16-bit access space) 4.4.3 valid strobes table 4.4 shows the data buses used and valid strobes for the access spaces. in a read, the rd signal is valid for both the upper and the lower half of the data bus. in a write, the hwr signal is valid for the upper half of the data bus, and the lwr signal for the lower half.
125 table 4.4 data buses used and valid strobes area access size read/ write address valid strobe upper data bus (d15 to d8) lower data bus (d7 to d0) 8-bit access byte read rd hwr rd hwr lwr rd hwr lwr
126 4.4.4 basic timing 8-bit, 2-state access space: figure 4.9 shows the bus timing for an 8-bit, 2-state access space. when an 8-bit access space is accessed, the upper half (d15 to d8) of the data bus is used. the lwr pin is fixed high. wait states cannot be inserted. bus cycle t 1 t 2 address bus csn as rd hwr lwr figure 4.9 bus timing for 8-bit, 2-state access space
127 8-bit, 3-state access space: figure 4.10 shows the bus timing for an 8-bit, 3-state access space. when an 8-bit access space is accessed, the upper half (d15 to d8) of the data bus is used. the lwr pin is fixed high. wait states can be inserted. bus cycle t 1 t 2 address bus csn as rd hwr lwr figure 4.10 bus timing for 8-bit, 3-state access space
128 16-bit, 2-state access space: figures 4.11 to 4.13 show bus timings for a 16-bit, 2-state access space. when a 16-bit access space is accessed, the upper half (d15 to d8) of the data bus is used for odd addresses, and the lower half (d7 to d0) for even addresses. wait states cannot be inserted. bus cycle t 1 t 2 address bus csn as rd hwr lwr figure 4.11 bus timing for 16-bit, 2-state access space (1) (even address byte access)
129 bus cycle t 1 t 2 address bus csn as rd hwr lwr figure 4.12 bus timing for 16-bit, 2-state access space (2) (odd address byte access)
130 bus cycle t 1 t 2 address bus csn as rd hwr lwr figure 4.13 bus timing for 16-bit, 2-state access space (3) (word access)
131 16-bit, 3-state access space: figures 4.14 to 4.16 show bus timings for a 16-bit, 3-state access space. when a 16-bit access space is accessed, the upper half (d15 to d8) of the data bus is used for the odd address, and the lower half (d7 to d0) for the even address. wait states can be inserted. bus cycle t 1 t 2 address bus csn as rd hwr lwr figure 4.14 bus timing for 16-bit, 3-state access space (1) (even address byte access)
132 bus cycle t 1 t 2 address bus csn as rd hwr lwr figure 4.15 bus timing for 16-bit, 3-state access space (2) (odd address byte access)
133 bus cycle t 1 t 2 address bus csn as rd hwr lwr figure 4.16 bus timing for 16-bit, 3-state access space (3) (word access)
134 4.4.5 wait control when accessing external space, the h8s/2678 series chip can extend the bus cycle by inserting one or more wait states (t w ). there are two ways of inserting wait states: (1) program wait insertion and (2) pin wait insertion using the wait pin. program wait insertion: from 0 to 3 wait states can be inserted automatically between the t 2 state and t 3 state on an individual area basis in 3-state access space, according to the settings in wtcra and wtcrb. pin wait insertion: setting the waite bit to 1 in bcr enables wait input by means of the wait pin. when external space is accessed in this state, a program wait is first inserted in accordance with the settings in wtcra and wtcrb. if the wait pin is low at the falling edge of ?in the last t 2 or t w state, another t w state is inserted. if the wait pin is held low, t w states are inserted until it goes high. this is useful when inserting seven or more t w states, or when changing the number of t w states to be inserted for different external devices. the waite bit setting applies to all areas. figure 4.17 shows an example of wait state insertion timing.
135 by program wait t 1 address bus as rd hwr lwr wait wait wait figure 4.17 example of wait state insertion timing the settings after a reset are: 3-state access, insertion of 7 program wait states, and wait input disabled.
136 4.4.6 read strobe ( rd ) timing the read strobe timing can be changed for individual areas by setting bits rdn7 to rdn0 to 1 in rdncr. when the dmac or exdmac is used in single mode, note that if the read strobe timing is changed by setting rdnn to 1, the rd timing will change relative to the rise of dack or edack . figure 4.18 shows an example of the timing when the read strobe timing is changed in basic bus 3- state access space. bus cycle t 1 t 2 address bus csn as rd rd dack edack figure 4.18 example of read strobe timing
137 4.4.7 extension of chip select ( cs ) assertion period some external i/o devices require a setup time and hold time between address and cs signals and strobe signals such as rd , hwr , and lwr . settings can be made in the csacr register to insert states in which only the cs , as , and address signals are asserted before and after a basic bus space access cycle. extension of the cs assertion period can be set for individual areas. with the cs assertion extension period in write access, the data setup and hold times are less stringent since the write data is output to the data bus. figure 4.19 shows an example of the timing when the cs assertion period is extended in basic bus 3-state access space. t h address bus t 1 t 2 t 3 t t bus cycle data bus hwr lwr rd csn as figure 4.19 example of timing when chip select assertion period is extended both extension state t h inserted before the basic bus cycle and extension state t t inserted after the basic bus cycle, or only one of these, can be specified for individual areas. insertion or non- insertion can be specified for the t h state with the upper 8 bits (csxh7 to csxh0) in the csacr register, and for the t t state with the lower 8 bits (csxt7 to csxt0).
138 4.5 dram interface 4.5.1 overview in the h8s/2678 series, external space areas 2 to 5 can be designated as dram space, and dram interfacing performed. the dram interface allows dram to be directly connected to the chip. a dram space of 2, 4, or 8 mbytes can be set by means of bits rmts2 to rmts0 in dramcr. burst operation is also possible, using fast page mode. 4.5.2 setting dram space areas 2 to 5 are designated as dram space by setting bits rmts2 to rmts0 in the dramcr register. the relation between the settings of bits rmts2 to rmts0 and dram space is shown in table 4.5. possible dram space settings are: one area (area 2), two areas (areas 2 and 3), four areas (areas 2 to 5), and continuous area (areas 2 to 5). table 4.5 dram space settings by bits rmts2 to rmts0 rmts2 rmts1 rmts0 area 5 area 4 area 3 area 2 0 0 1 normal space normal space normal space dram space 1 0 normal space normal space dram space dram space 1 dram space dram space dram space dram space 10 * reserved reserved reserved reserved 10 (setting prohibited) (setting prohibited) (setting prohibited) (setting prohibited) 1 continuous dram space continuous dram space continuous dram space continuous dram space * : don t care with continuous dram space, ras2 is valid. the bus specifications (bus width, number of wait states, etc.) for continuous dram space conform to the settings for area 2.
139 4.5.3 address multiplexing with dram space, the row address and column address are multiplexed. in address multiplexing, the size of the shift of the row address is selected with bits mxc2 to mxc0 in dramcr. table 4.6 shows the correspondence between the settings of mxc2 to mxc0 and the shift size. table 4.6 address multiplexing settings by bits mxc2 to mxc0 dramcr address pins mxc2 mxc1 mxc0 shift size a23 to a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 row address 0008 bits a23 to a16 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 1 9 bits a23 to a16 a15 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 1 0 10 bits a23 to a16 a15 a14 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 1 11 bits a23 to a16 a15 a14 a13 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 1 reserved (setting prohibited) column address a23 to a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 4.5.4 data bus if a bit in abwcr corresponding to an area designated as dram space is set to 1, that area is designated as 8-bit dram space; if the bit is cleared to 0, the area is designated as 16-bit dram space. in 16-bit dram space, 16-bit configuration dram can be connected directly. in 8-bit dram space the upper half of the data bus, d15 to d8, is enabled, while in 16-bit dram space both the upper and lower halves of the data bus, d15 to d0, are enabled. access sizes and data alignment are the same as for the basic bus interface: see section 4.4.2, data size and data alignment.
140 4.5.5 pins used for dram interface table 4.7 shows the pins used for dram interfacing and their functions. table 4.7 dram interface pins pin with dram setting name i/o function hwr we cs2 ras2 cs3 ras3 cs4 ras4 cs5 ras5 ucas ucas lcas lcas rd oe oe wait wait
141 4.5.6 basic timing figure 4.20 shows the basic access timing for dram space. the four states of the basic timing consist of one t p (precharge cycle) state, one t r (row address output cycle) state, and the t c1 and t c2 (column address output cycle) states. t p rasn csn ucas lcas we hwr oe rd we hwr oe rd figure 4.20 dram basic access timing (rast = 0, cast = 0) when dram space is accessed, the rd signal is output as the oe signal for dram. when connecting dram provided with an edo page mode, the oe signal should be connected to the oe pin of the dram. setting the oee bit to 1 in the dramcr register enables the oe signal for dram space to be output from a dedicated oe pin. in this case, the oe signal for dram space is
142 output from both the rd pin and the oe pin, but in external read cycles for other than dram space, the signal is output only from the rd pin. 4.5.7 column address output cycle control the column address output cycle can be changed from 2 states to 3 states by setting the cast bit to 1 in the dramcr register. use the setting that gives the optimum specification values ( cas pulse width, etc.) according to the dram connected and the operating frequency of the chip. figure 4.21 shows an example of the timing when a 3-state column address output cycle is selected. t p rasn csn ucas lcas we hwr oe rd we hwr oe rd figure 4.21 example of access timing with 3-state column address output cycle (rast = 0)
143 4.5.8 row address output cycle control if the rast bit is set to 1 in the dramcr register, the ras signal goes low from the beginning of the t r state, and the row address hold time and dram read access time are changed relative to the fall of the ras signal. use the optimum setting according to the dram connected and the operating frequency of the chip. figure 4.22 shows an example of the timing when the ras signal goes low from the beginning of the t r state. t p rasn csn ucas lcas we hwr oe rd we hwr oe rd figure 4.22 example of access timing when ras signal goes low from beginning of t r state (cast = 0)
144 if a row address hold time or read access time is necessary, making a setting in bits rcd1 and rcd0 in the draccr register allows from one to three t rw states, in which row address output is maintained, to be inserted between the t r cycle, in which the ras signal goes low, and the t c1 cycle, in which the column address is output. use the setting that gives the optimum row address signal hold time relative to the fall of the ras signal according to the dram connected and the operating frequency of the chip. figure 4.23 shows an example of the timing when one t rw state is set. t p rasn csn ucas lcas we hwr oe rd we hwr oe rd figure 4.23 example of timing with one row address output maintenance state (rast = 0, cast = 0)
145 4.5.9 precharge state control when dram is accessed, a ras precharge time must be secured. with the h8s/2678 series, one t p state is always inserted when dram space is accessed. from one to four t p states can be selected by setting bits tpc1 and tpc0 in draccr. set the optimum number of t p cycles according to the dram connected and the operating frequency of the chip. figure 4.24 shows the timing when two tp states are inserted. the setting of bits tpc1 and tpc0 is also valid for t p states in refresh cycles. t p1 rasn csn ucas lcas we hwr oe rd we hwr oe rd figure 4.24 example of timing with two-state precharge cycle (rast = 0, cast = 0)
146 4.5.10 wait control there are two ways of inserting wait states in a dram access cycle: (1) program wait insertion and (2) pin wait insertion using the wait pin. wait states are inserted to extend the cas assertion period in a read access to dram space, and to extend the write data setup time relative to the falling edge of cas in a write access. program wait insertion: when the bit in astcr corresponding to an area designated as dram space is set to 1, from 0 to 7 wait states can be inserted automatically between the t c1 state and t c2 state, according to the settings in registers wtcra and wtcrb. pin wait insertion: when the waite bit in the bcr register is set to 1 and the astcr bit is set to 1, wait input by means of the wait pin is enabled. when dram space is accessed in this state, a program wait (t w ) is first inserted. if the wait pin is low at the falling edge of ?in the last t c1 or t w state, another t w state is inserted. if the wait pin is held low, t w states are inserted until it goes high. figures 4.25 and 4.26 show examples of wait state insertion timing in the case of 2-state and 3- state column address output cycles.
147 by program wait t p address bus wait wait rasn csn ucas lcas ucas lcas we hwr oe rd we hwr oe rd wait figure 4.25 example of wait state insertion timing (1) (2-state column address output)
148 by program wait t p address bus wait wait rasn csn ucas lcas ucas lcas we hwr oe rd we hwr oe rd wait figure 4.26 example of wait state insertion timing (2) (3-state column address output)
149 4.5.11 byte access control when dram with a 16 configuration is connected, the 2-cas access method is used for the control signals needed for byte access. figure 4.27 shows the control timing for 2-cas access, and figure 4.28 shows an example of 2- cas dram connection. t p high-z rasn csn ucas lcas we hwr oe rd figure 4.27 2-cas control timing (upper byte write access: rast = 0, cast = 0)
150 h8s/2678 series chip (address shift size set to 10 bits) ras cs ras ucas ucas lcas lcas hwr we we rd oe oe figure 4.28 example of 2-cas dram connection 4.5.12 burst operation with dram, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, a fast page mode is also provided which can be used when making consecutive accesses to the same row address. this mode enables fast (burst) access of data by simply changing the column address after the row address has been output. burst access can be selected by setting the be bit to 1 in dramcr. burst access (fast page mode) operation timing: figures 4.29 and 4.30 show the operation timing for burst access. when there are consecutive access cycles for dram space, the cas signal and column address output cycles (two states) continue as long as the row address is the same for consecutive access cycles. the row address used for the comparison is set with bits mxc2 to mxc0 in dramcr.
151 t p t r t c1 t c2 t c1 t c2 rasn csn ucas lcas we hwr oe rd we hwr oe rd figure 4.29 operation timing in fast page mode (1) (rast = 0, cast = 0)
152 t p t r t c1 t c2 t c3 t c1 t c2 t c3 rasn csn ucas lcas we hwr oe rd we hwr oe rd figure 4.30 operation timing in fast page mode (2) (rast = 0, cast = 1) the bus cycle can also be extended in burst access by inserting wait states. the wait state insertion method and timing are the same as for full access. for details see section 4.5.10, wait control. ras down mode and ras up mode: even when burst operation is selected, it may happen that access to dram space is not continuous, but is interrupted by access to another space. in this case, if the ras signal is held low during the access to the other space, burst operation can be resumed when the same row address in dram space is accessed again. ? ras down mode to select ras down mode, set both the rcdm bit and the be bit to 1 in dramcr. if access to dram space is interrupted and another space is accessed, the ras signal is held low during the access to the other space, and burst access is performed when the row address of the next dram space access is the same as the row address of the previous dram space access. figure 4.31 shows an example of the timing in ras down mode. note, however, that the ras signal will go high if: ? a refresh operation is initiated in the ras down state ? self-refreshing is performed ? the chip enters software standby mode
153 ? the external bus is released ? the rcdm bit or be bit is cleared to 0 if a transition is made to the all-module-clocks-stopped mode in the ras down state, the clock will stop with ras low. to enter the all-module-clocks-stopped mode with ras high, the rcdm bit must be cleared to 0 before executing the sleep instruction. normal space read dram space read t p t r t c1 t c2 t 1 t 2 dram space read t c1 t c2 note: n = 2 to 5 rasn csn ucas lcas rd oe figure 4.31 example of operation timing in ras down mode (rast = 0, cast = 0) ? ras up mode to select ras up mode, clear the rcdm bit to 0 in dramcr. each time access to dram space is interrupted and another space is accessed, the ras signal goes high again. burst operation is only performed if dram space is continuous. figure 4.32 shows an example of the timing in ras up mode.
154 normal space read dram space read t p t r t c1 t c2 t 1 t 2 dram space read t c1 t c2 note: n = 2 to 5 rasn csn ucas lcas rd oe figure 4.32 example of operation timing in ras up mode (rast = 0, cast = 0) 4.5.13 refresh control the h8s/2678 series is provided with a dram refresh control function. cas-before-ras (cbr) refreshing is used. in addition, self-refreshing can be executed when the chip enters the software standby state. refresh control is enabled when any area is designated as dram space in accordance with the setting of bits rmts2 to rmts0 in the dramcr register. cas-before-ras (cbr) refreshing: to select cbr refreshing, set the rfshe bit to 1 in dramcr. with cbr refreshing, rtcnt counts up using the input clock selected by bits rtck2 to rtck0 in refcr, and when the count matches the value set in rtcor (compare match), refresh control is performed. at the same time, rtcnt is reset and starts counting up again from h'00.
155 refreshing is thus repeated at fixed intervals determined by rtcor and bits rtck2 to rtck0. set a value in rtcor and bits rtck2 to rtck0 that will meet the refreshing interval specification for the dram used. when bits rtck2 to rtck0 are set, rtcnt starts counting up. rtcnt and rtcor settings should therefore be completed before setting bits rtck2 to rtck0. rtcnt operation is shown in figure 4.33, compare match timing in figure 4.34, and cbr refresh timing in figure 4.35. when the cbrm bit is cleared to 0, access to external space other than dram space is performed in parallel during the cbr refresh period. rtcor h'00 refresh request rtcnt figure 4.33 rtcnt operation rtcnt n rtcor n h'00 refresh request signal and cmf bit setting signal figure 4.34 compare match timing
156 t rp csn rasn ucas lcas figure 4.35 cbr refresh timing a setting can be made in bits rcw1 and rcw0 to delay ras signal output by one to three cycles. use bits rlw1 and rlw0 to adjust the width of the ras signal. the settings of bits rcw1, rcw0, rlw1, and rlw0 are valid only in refresh operations. figure 4.36 shows the timing when bits rcw1 and rcw0 are set to 0 and 1, respectively. t rp csn rasn ucas lcas figure 4.36 cbr refresh timing (rcw1 = 0, rcw0 = 1, rlw1 = 0, rlw0 = 0) depending on the dram used, modification of the we signal may not be permitted during the refresh period. in this case, the cbrm bit should be set to 1. the bus controller will then insert refresh cycles in appropriate breaks between bus cycles. figure 4.37 shows an example of the timing when the cbrm bit is set to 1. in this case the cs signal is not controlled, and retains its value prior to the start of the refresh period.
157 a23 to a0 cs as rd hwr we cas ras figure 4.37 example of cbr refresh timing (cbrm = 1) self-refreshing: a self-refresh mode (battery backup mode) is provided for dram as a kind of standby mode. in this mode, refresh timing and refresh addresses are generated within the dram. to select self-refreshing, set the rfshe bit and slfrf bit to 1 in the refcr register. when a sleep instruction is executed to enter software standby mode, the cas and ras signals are output and dram enters self-refresh mode, as shown in figure 4.38. when software standby mode is exited, the slfrf bit is cleared to 0 and self-refresh mode is exited automatically. if a cbr refresh request occurs when making a transition to software standby mode, cbr refreshing is executed, then self-refresh mode is entered. when using self-refresh mode, the ope bit must not be cleared to 0 in the sbycr register.
158 t rp t rr ucas lcas hwr we csn rasn figure 4.38 self-refresh timing in some drams provided with a self-refresh mode, the ras signal precharge time after self- refreshing is longer than the normal precharge time. a setting can be made in bits tpcs2 to tpcs0 in the refcr register to make the precharge time after self-refreshing from 1 to 7 states longer than the normal precharge time. in this case, too, normal precharging is performed according to the setting of bits tpc1 and tpc0 in the draccr register, and therefore a setting should be made to give the optimum post-self-refresh precharge time, including this time. figure 4.39 shows an example of the timing when the precharge time after self-refreshing is extended by 2 states.
159 dram space write t rc3 t rp1 t rp2 t p t r software standby t c1 t c2 note: n = 2 to 5 rasn csn ucas lcas oe rd wr hwr figure 4.39 example of timing when precharge time after self-refreshing is extended by 2 states refreshing and all-module-clocks-stopped mode: in the h8s/2678 series, if the acse bit is set to 1 in the mstpcr register, and then a sleep instruction is executed with the setting for all supporting module clocks to be stopped (mstpcr = h'ffff) or for operation of the 8-bit timer module alone (mstpcr = h'fffe), and a transition is made to the sleep state, the all-module- clocks-stopped mode is entered, in which the bus controller and i/o port clocks are also stopped. as the bus controller clock is also stopped in this mode, cbr refreshing is not executed. if dram is connected externally and dram data is to be retained in sleep mode, the acse bit must be cleared to 0 in mstpcr. 4.5.14 dmac and exdmac single address transfer mode and dram interface when burst mode is selected on the dram interface, the dack and edack output timing can be selected with the dds and edds bits. when dram space is accessed in dmac/exdmac single address mode at the same time, these bits select whether or not burst access is to be performed.
160 when dds = 1 or edds = 1: burst access is performed by determining the address only, irrespective of the bus master. with the dram interface, the dack or edack output goes low from the t c1 state. figure 4.40 shows the dack / edack output timing for the dram interface when dds = 1 or edds = 1. t p rasn csn ucas lcas we hwr oe rd we hwr oe rd dack edack figure 4.40 example of dack / edack output timing when dds = 1 or edds = 1 (1) (rast = 0, cast = 0)
161 when dds = 0 or edds = 0: when dram space is accessed in dmac or exdmac single address transfer mode, full access (normal access) is always performed. with the dram interface, the dack or edack output goes low from the t r state. in modes other than dmac or exdmac single address transfer mode, burst access can be used when accessing dram space. figure 4.41 shows the dack / edack output timing for the dram interface when dds = 0 or edds = 0. t p rasn csn ucas lcas we hwr oe rd we hwr oe rd dack edack figure 4.41 example of dack / edack output timing when dds = 0 or edds = 0 (2) (rast = 0, cast = 1)
162 4.6 burst rom interface 4.6.1 overview in the h8s/2678 series, external space areas 0 and 1 can be designated as burst rom space, and burst rom interfacing performed. the burst rom space interface enables rom with burst access capability to be accessed at high speed. areas 1 and 0 can be designated as burst rom space by means of bits bsrm1 and bsrm0 in bromcr. consecutive burst accesses of a maximum or 4, 8, 16, or 32 words can be performed, according to the bromcr register setting. from 1 to 8 states can be selected for burst access. settings can be made independently for area 0 and area 1. in burst rom interface space, burst access covers only cpu read accesses. 4.6.2 basic timing the number of states in the initial cycle (full access) on the burst rom interface is determined by the basic bus interface settings in the astcr, abwcr, wtcra, wtcrb, and csacrh registers. when area 0 or area 1 is designated as burst rom interface space, the settings in the rdcnr and csacrl registers are ignored. from 1 to 8 states can be selected for the burst cycle, according to the settings of bits bsts02 to bsts00 and bsts12 to bsts10 in bromcr. wait states cannot be inserted. burst access of up to 32 words is performed, according to the settings of bits bsts01, bsts00, bsts11, and bsts10 in bromcr the basic access timing for burst rom space is shown in figures 4.42 and 4.43. figure 4.42 shows the timing when astn = 1 and a 2-state burst cycle is set, and figure 4.43 shows the timing when astn = 0 and a 1-state burst cycle is set.
163 t 1 upper address bus lower address bus csn as rd figure 4.42 example of burst rom access timing (1) (astn = 1, 2-state burst cycle)
164 t 1 upper address bus lower address bus csn as rd figure 4.43 example of burst rom access timing (2) (astn = 0, 1-state burst cycle) 4.6.3 wait control as with the basic bus interface, either (1) program wait insertion or (2) pin wait insertion using the wait pin can be used in the initial cycle (full access) on the burst rom interface. see section 4.4.5, wait control. wait states cannot be inserted in a burst cycle. 4.6.4 write access when a write access to burst rom interface space is executed, burst access is interrupted at that point and the write access is executed in line with the basic bus interface settings. write accesses are not performed in burst mode even though burst rom space is designated.
165 4.7 idle cycle 4.7.1 operation when the h8s/2678 series chip accesses external space, it can insert an idle cycle (t i ) between bus cycles in the following two cases: (1) when read accesses in different areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle. insertion of a 1- state or 2-state idle cycle can be selected with the idlc bit in the bcr register. by inserting an idle cycle it is possible, for example, to avoid data collisions between rom, etc., with a long output floating time, and high-speed memory, i/o interfaces, and so on. consecutive reads in different areas: if consecutive reads in different areas occur while the icis1 bit is set to 1 in the bcr register, an idle cycle is inserted at the start of the second read cycle. figure 4.44 shows an example of the operation in this case. in this example, bus cycle a is a read cycle for rom with a long output floating time, and bus cycle b is a read cycle for sram, each being located in a different area. in (a), an idle cycle is not inserted, and a collision occurs in bus cycle b between the read data from rom and that from sram. in (b), an idle cycle is inserted, and a data collision is prevented. t 1 address bus rd y data bus t 2 t 3 t 1 t 2 bus cycle b long output floating time data collision (a) idle cycle not inserted (icis1 = 0) t 1 address bus rd (b) idle cycle inserted (icis1 = 1 (initial value)) t 2 cs cs cs cs figure 4.44 example of idle cycle operation (1) (consecutive reads in different areas)
166 write after read: if an external write occurs after an external read while the icis0 bit is set to 1 in the bcr register, an idle cycle is inserted at the start of the write cycle. figure 4.45 shows an example of the operation in this case. in this example, bus cycle a is a read cycle for rom with a long output floating time, and bus cycle b is a cpu write cycle. in (a), an idle cycle is not inserted, and a collision occurs in bus cycle b between the read data from rom and the cpu write data. in (b), an idle cycle is inserted, and a data collision is prevented. t 1 address bus rd (a) idle cycle not inserted (icis0 = 0) t 1 address bus rd (b) idle cycle inserted (icis0 = 1 (initial value)) t 2 hwr hwr cs cs cs cs y figure 4.45 example of idle cycle operation (2) (write after read) relationship between chip select ( cs ) signal and read ( rd ) signal: depending on the system? load conditions, the rd signal may lag behind the cs signal. an example is shown in figure 4.46. in this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle a rd signal and the bus cycle b cs signal. setting idle cycle insertion, as in (b), however, will prevent any overlap between the rd and cs signals. in the initial state after reset release, idle cycle insertion (b) is set.
167 t 1 address bus rd cs rd (a) idle cycle not inserted (icis1 = 0) t 1 address bus bus cycle a t 2 t 3 t i t 1 bus cycle b (b) idle cycle inserted (icis1 = 1 (initial value)) t 2 cs cs rd cs cs figure 4.46 relationship between chip select ( cs ) and read ( rd ) idle cycle in case of dram space access after normal space access: in a dram space access following a normal space access, the settings of bits icis1, icis0, and idlc are valid. however, in the case of consecutive reads in different areas, for example, if the second read is a full access to dram space, only a t p cycle is inserted, and a t i cycle is not. the timing in this case is shown figure 4.47. t 1 address bus rd figure 4.47 example of dram full access after external read (cast = 0)
168 in burst access in ras down mode, the settings of bits icis1, icis0, and idlc are valid and an idle cycle is inserted. the timing in this case is illustrated in figures 4.48 and 4.49. t p address bus rd ras ucas lcas figure 4.48 example of idle cycle operation in ras down mode (1) (consecutive reads in different areas) (idlc = 0, rast = 0, cast = 0)
169 t p address bus rd ras hwr ucas lcas figure 4.49 example of idle cycle operation in ras down mode (2) (read after write) (idlc = 0, rast = 0, cast = 0) idle cycle in case of normal space access after dram space access: while the drmi bit is cleared to 0 in the draccr register, idle cycle insertion after dram space access is disabled. idle cycle insertion after dram space access can be enabled by setting the drmi bit to 1. the conditions and number of states of the idle cycle to be inserted are in accordance with the settings of bits icis1, icis0, and idlc are valid. figures 4.50 and 4.51 show examples of idle cycle operation when the drmi bit is set to 1. when the drmi bit is cleared to 0, an idle cycle is not inserted after dram space access even if bits icis1 and icis0 are set to 1.
170 t p address bus rd ras ucas lcas figure 4.50 example of idle cycle operation after dram access (1) (consecutive reads in different areas) (idlc = 0, rast = 0, cast = 0) t p address bus rd ras hwr lwr ucas lcas figure 4.51 example of idle cycle operation after dram access (2) (read after write) (idlc = 0, rast = 0, cast = 0)
171 table 4.8 shows when idle cycles are inserted in the case of mixed accesses to normal space and dram space. table 4.8 idle cycles in mixed accesses to normal space and dram space previous access next access icis1 icis0 drmi idlc idle cycle normal space read normal space read 1 0 1 state inserted (different area) 1 2 states inserted normal space read dram space read 1 0 1 state inserted 1 2 states inserted normal space read normal space write 1 0 1 state inserted 1 2 states inserted normal space read dram space write 1 0 1 state inserted 1 2 states inserted dram space read normal space read 1 0 disabled 1 0 1 state inserted 1 2 states inserted dram space read dram space read 1 0 disabled 1 0 1 state inserted 1 2 states inserted dram space read normal space write 10 disabled 1 0 1 state inserted 1 2 states inserted dram space read dram space write 10 disabled 1 0 1 state inserted 1 2 states inserted setting the drmi bit to 1 enables an idle cycle to be inserted in the case of consecutive read and write operations in dram space burst access. figure 4.52 shows an example of the timing for idle cycle insertion in the case of consecutive read and write accesses to dram space.
172 t p address bus idle cycle data bus t r t c1 t c2 dram space write dram space read t c2 t i t c1 rasn csn ucas lcas we hwr oe rd figure 4.52 example of timing for idle cycle insertion in case of consecutive read and write accesses to dram space in ras down mode
173 4.7.2 pin states in idle cycle table 4.9 shows the pin states in an idle cycle. table 4.9 pin states in idle cycle pins pin state a23 to a0 contents of following bus cycle d15 to d0 high impedance csn * 1, * 2 ucas lcas * 2 as rd oe hwr lwr dackn edackn 4.8 write data buffer function the h8s/2678 series has a write data buffer function for the external data bus. using the write data buffer function enables external writes and dma single address mode transfers to be executed in parallel with internal accesses. the write data buffer function is made available by setting the wdbe bit to 1 in the bcr register. figure 4.53 shows an example of the timing when the write data buffer function is used. when this function is used, if an external write or dma single address mode transfer continues for two states or longer, and there is an internal access next, an external write only is executed in the first state, but from the next state onward an internal access (on-chip memory or internal i/o register read/write) is executed in parallel with the external write rather than waiting until it ends.
174 t 1 internal address bus a23 to a0 external write cycle hwr lwr csn figure 4.53 example of timing when write data buffer function is used 4.9 bus release 4.9.1 overview the h8s/2678 series chip can release the external bus in response to a bus request from an external device. in the external bus released state, internal bus masters (except the exdmac) continue to operate as long as there is no external access. if any of the following requests are issued in the external bus released state, the breqo signal can be driven low to output a bus request externally. ? when an internal bus master wants to perform an external access ? when a refresh request is generated ? when a sleep instruction is executed to place the chip in software standby mode or all- module-clocks-stopped mode
175 4.9.2 operation in externally expanded mode, the bus can be released to an external device by setting the brle bit to 1 in the bcr register. driving the breq pin low issues an external bus request to the h8s/2678 series chip. when the breq pin is sampled, at the prescribed timing the back pin is driven low, and the address bus, data bus, and bus control signals are placed in the high- impedance state, establishing the external bus released state. in the external bus released state, an internal bus master can perform accesses using the internal bus. when an internal bus master wants to make an external access, it temporarily defers initiation of the bus cycle, and waits for the bus request from the external bus master to be canceled. if a refresh request is generated in the external bus released state, or if a sleep instruction is executed to place the chip in software standby mode or all-module-clocks-stopped mode, refresh control and software standby or all-module-clocks-stopped control is deferred until the bus request from the external bus master is canceled. if the breqoe bit is set to 1 in the bcr register, the breqo signal can be driven low when any of the following requests are issued, to request cancellation of the bus request externally. ? when an internal bus master wants to perform an external access ? when a refresh request is generated ? when a sleep instruction is executed to place the chip in software standby mode or all- module-clocks-stopped mode when the breq pin is driven high, the back pin is driven high at the prescribed timing and the external bus released state is terminated. if an external bus release request and external access occur simultaneously, the order of priority is as follows: (high) external bus release > external access by internal bus master (low) if a refresh request and external bus release request occur simultaneously, the order of priority is as follows: (high) refresh > external bus release (low)
176 4.9.3 pin states in external bus released state table 4.10 shows pin states in the external bus released state. table 4.10 pin states in bus released state pins pin state a23 to a0 high impedance d15 to d0 high impedance csn ucas lcas as rd oe hwr lwr dackn edackn
177 4.9.4 transition timing figure 4.54 shows the timing for transition to the bus released state. cpu cycle external bus released state external space access cycle t 1 t 2 address bus hwr lwr breq back breqo as rd breq . [2] bus control signals temporarily return to high level at end of external space access cycle. minimum of 1 state after breq back breq breq back breqo breqo back breqo breqo figure 4.54 bus released state transition timing
178 4.9.5 usage notes external bus release function and all-module-clocks-stopped mode: in the h8s/2678 series, if the acse bit is set to 1 in the mstpcr register, and then a sleep instruction is executed with the setting for all supporting module clocks to be stopped (mstpcr = h'ffff) or for operation of the 8-bit timer module alone (mstpcr = h'fffe), and a transition is made to the sleep state, the all-module-clocks-stopped mode is entered in which the clock is also stopped for the bus controller and i/o ports. in this state, the external bus release function is halted. to use the external bus release function in sleep mode, the acse bit in mstpcr must be cleared to 0. conversely, if a sleep instruction to place the chip in all-module-clocks-stopped mode is executed in the external bus released state, the transition to all-module-clocks-stopped mode is deferred until after the bus is recovered. external bus release function and software standby: in the h8s/2678 series, internal bus master operation does not stop even while the bus is released, as long as the program is running in on-chip rom, etc., and no external access occurs. if a sleep instruction to place the chip in software standby mode is executed while the external bus is released, the transition to software standby mode is deferred until after the bus is recovered. also, since clock oscillation halts in software standby mode, if breq goes low in this mode, indicating an external bus release request, the request cannot be answered until the chip has recovered from the software standby state. external bus release function and cbr refreshing: cbr refreshing cannot be executed while the external bus is released. setting the breqoe bit to 1 in the bcr register beforehand enables the breqo signal to be output when a cbr refresh request is issued. breqo output timing: when the breqoe bit is set to 1 and the breqo signal is output, breqo may go low before the back signal. this will occur if the next external access request or cbr refresh request occurs while internal bus arbitration is in progress after the chip samples a low level of breq .
179 4.10 bus arbitration 4.10.1 overview the h8s/2678 series has a bus arbiter that arbitrates bus master operations. there are four bus masters?he cpu, dtc, dmac, and exdmac?hat perform read/write operations when they have possession of the bus. each bus master requests the bus by means of a bus request signal. the bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal. the selected bus master then takes possession of the bus and begins its operation. 4.10.2 operation the bus arbiter monitors the bus masters?bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master making the request. if there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. when a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. the order of priority of the bus masters is as follows: (high) exdmac > dmac > dtc > cpu (low) an external access by an internal bus master (except the exdmac) and (1) external bus release, (2) a refresh when the cbrm bit is 0, and (3) an external bus access by the exdmac can be executed in parallel. if an external bus release request, a refresh request, and an external access by an internal bus master occur simultaneously, the order of priority is as follows: (high) refresh > exdmac > external bus release (low) (high) external bus release > external access by internal bus master except exdmac (low) as a refresh when the cbrm bit is 0 and an external access other than to dram space by an internal bus master can be executed simultaneously, there is no relative order of priority for these two operations.
180 4.10.3 bus transfer timing even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. there are specific times at which each bus master can relinquish the bus. cpu: the cpu is the lowest-priority bus master, and if a bus request is received from the dtc, dmac, or exdmac, the bus arbiter transfers the bus to the bus master that issued the request. the timing for transfer of the bus is as follows: ? the bus is transferred at a break between bus cycles. however, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the component operations. ? with bit manipulation instructions such as bset and bclr, the sequence of operations is: data read (read), relevant bit manipulation operation (modify), write-back (write). the bus is not transferred during this read-modify-write cycle, which is executed as a series of bus cycles. ? if the cpu is in sleep mode, the bus is transferred immediately. dtc: the dtc sends the bus arbiter a request for the bus when an activation request is generated. the dtc can release the bus after a vector read, a register information read (3 states), a single data transfer, or a register information write (3 states). it does not release the bus during a register information read (3 states), a single data transfer, or a register information write (3 states). dmac: the dmac sends the bus arbiter a request for the bus when an activation request is generated. in the case of an external request in short address mode or normal mode, and in cycle steal mode, the dmac releases the bus after a single transfer. in block transfer mode, it releases the bus after transfer of one block, and in burst mode, after completion of the transfer. however, in the event of an exdmac or external bus release request, which have a higher priority than the dmac, the bus may be transferred to the bus master even if burst transfer is in progress. exdmac: the exdmac sends the bus arbiter a request for the bus when an activation request is generated. as the exdmac is used exclusively for transfers to and from the external bus, if the bus is transferred to the exdmac, internal accesses by other internal bus masters are still executed in parallel. in normal transfer mode or cycle steal transfer mode, the exdmac releases the bus after a single transfer.
181 in block transfer mode, it releases the bus after transfer of one block, and in burst mode, after completion of the transfer. by setting the bgup bit to 1 in the edmdr register, it is possible to specify temporary release of the bus in the event of an external access request from an internal bus master. for details see section 7, exdma controller, in the h8s/2678 series hardware manual. external bus release: when the breq pin goes low and an external bus release request is issued while the brle bit is set to 1 in the bcr register, a bus request is sent to the bus arbiter. external bus release can be performed on completion of an external bus cycle. 4.11 bus controller operation in a reset in a reset, the chip, including the bus controller, enters the reset state immediately, and any executing bus cycle is aborted.
182
183 section 5 i/o ports 5.1 overview the h8s/2678 series has fifteen i/o ports (ports 1 to 3, p50 to p53, 6 to 8, and a to h), and two input-only ports (port 4 and p54 to p57). table 5.1 summarizes the port functions. the pins of each port also have other functions. each port includes a data direction register (ddr) that controls input/output (not provided for the input-only ports), a data register (dr) that stores output data, and a port register (port) used to read the pin states. ports a to e have a built-in mos input pull-up function, and in addition to dr and ddr, have a mos input pull-up control register (pcr) to control the on/off status of mos input pull-ups. ports 3 and a include an open-drain control register (odr) that controls the on/off status of the output buffer pmos. ports a to h can drive a single ttl load and 50 pf capacitive load, and ports 1, 2, 3, 5 (p50 to p53), 6, 7, and 8 can drive a single ttl load and 30 pf capacitive load. ports 1 and 2 have schmitt-trigger input circuits. ports 5, 6, 8, f (pf1, pf2), and h (ph2, ph3) are schmitt-trigger inputs when used as irq inputs.
184 table 5.1 port functions port description pins modes 1, 2, 5, 6 mode 4 mode 7 port 1 ? 8-bit i/o port ? schmitt- trigger input p17/po15/tiocb2/ tclkd/ edrak3 p16/po14/tioca2/ edrak2 2-bit i/o port also functioning as exdma controller output pins ( edrak3 , edrak2 ), tpu i/o pins (tclkd, tioca2, tiocb2), and ppg output pins (po15, po14) ? when expe = 0 (after reset): 2-bit i/o port also functioning as tpu i/o pins (tclkd, tioca2, tiocb2) and ppg output pins (po15, po14) ? when expe = 1: 2-bit i/o port also functioning as exdma controller output pins ( edrak3 , edrak2 ), tpu i/o pins (tclkd, tioca2, tiocb2), and ppg output pins (po15, po14) p15/po13/tiocb1/ tclkc p14/po12/tioca1 p13/po11/tiocd0/ tclkb p12/po10/tiocc0/ tclka p11/po9/tiocb0 p10/po8/tioca0 6-bit i/o port also functioning as tpu i/o pins (tclka, tclkb, tclkc, tioca0, tiocb0, tiocc0, tiocd0, tioca1, tiocb1) and ppg output pins (po13 to po8) port 2 ? 8-bit i/o port ? schmitt- trigger input p27/po7/tiocb5/ irq15 / edrak1 p26/po6/tioca5/ irq14 / edrak0 2-bit i/o port also functioning as exdma controller output pins ( edrak1 , edrak0 ), tpu i/o pins (tioca5, tiocb5), interrupt input pins ( irq15 , irq14 ), and ppg output pins (po7, po6) ? when expe = 0 (after reset): 2-bit i/o port also functioning as tpu i/o pins (tioca5, tiocb5), interrupt input pins ( irq15 , irq14 ), and ppg output pins (po7, po6) ? when expe = 1: 2-bit i/o port also functioning as exdma controller output pins ( edrak1 , edrak0 ), tpu i/o pins (tioca5, tiocb5), interrupt input pins ( irq15 , irq14 ), and ppg output pins (po7, po6)
185 port description pins modes 1, 2, 5, 6 mode 4 mode 7 port 2 ? 8-bit i/o port ? schmitt- trigger input p25/po5/tiocb4/ irq13 p24/po4/tioca4/ irq12 p23/po3/tiocd3/ irq11 p22/po2/tiocc3/ irq10 p21/po1/tiocb3/ irq9 p20/po0/tioca3/ irq8 6-bit i/o port also functioning as tpu i/o pins (tioca3, tiocb3, tiocc3, tiocd3, tioca4, tiocb4), interrupt input pins ( irq13 to irq8 ), and ppg output pins (po5 to po0) port 3 ? 6-bit i/o port ? open-drain output capability p35/sck1/ oe ? when oee = 1 and oes =0: oe output ? otherwise (after reset): i/o port also functioning as sci (channel 1) i/o pin (sck1) ? when expe = 0 (after reset): i/o port also functioning as sci (channel 1) i/o pin (sck1) ? when expe = 1: oe output when oee = 1 and oes =0 ? otherwise: i/o port also functioning as sci (channel 1) i/o pin (sck1) p34/sck0 p33/rxd1 p32/rxd0/irrxd p31/txd1 p30/txd0/irtxd 5-bit i/o port also functioning as sci (channels 0 and 1) i/o pins (sck0, rxd1, rxd0/irrxd, txd1, txd0/irtxd) port 4 ? 8-bit i/o port p47/an7/da1 p46/an6/da0 p45/an5 p44/an4 p43/an3 p42/an2 p41/an1 p40/an0 8-bit input port also functioning as a/d converter analog inputs (an7 to an0) and d/a converter analog outputs (da1, da0)
186 port description pins modes 1, 2, 5, 6 mode 4 mode 7 port 5 ? 4-bit i/o port ? 4-bit input port p57/an15/da3/ irq7 p56/an14/da2/ irq6 p55/an13/ irq5 p54/an12/ irq4 4-bit input port also functioning as a/d converter analog inputs (an15 to an12), d/a converter analog outputs (da3, da2), and interrupt input pins ( irq7 to irq4 ) p53/ adtrg / irq3 p52/sck2/ irq2 p51/rxd2/ irq1 p50/txd2/ irq0 4-bit i/o port also functioning as a/d converter input pin ( adtrg ), sci (channel 2) i/o pins (txd2, rxd2, sck2), and interrupt input pins ( irq3 to irq0 ) port 6 ? 6-bit i/o port p65/tmo1/ dack1 / irq13 p64/tmo0/ dack0 / irq12 p63/tmci1/ tend1 / irq11 p62/tmci0/ tend0 / irq10 p61/tmri1/ dreq1 / irq9 p60/tmri0/ dreq0 / irq8 ? when dmacs = 0 (after reset): 6-bit i/o port also functioning as dma controller i/o pins ( dack1 , dack0 , tend1 , tend0 , dreq1 , dreq0 ), 8-bit timer (channels 0 and 1) pins (tmo1, tmo0, tmci1, tmci0, tmri1, tmri0), and interrupt input pins ( irq13 to irq8 ) ? when dmacs = 1: 6-bit i/o port also functioning as 8-bit timer (channels 0 and 1) pins (tmo1, tmo0, tmci1, tmci0, tmri1, tmri0) and interrupt input pins ( irq13 to irq8 ) port 7 ? 6-bit i/o port p75/ dack1 / edack1 p74/ dack0 / edack0 p73/ tend1 / etend1 p72/ tend0 / etend0 p71/ dreq1 / edreq1 p70/ dreq0 / edreq0 ? when dmacs = 0 (after reset): 6-bit i/o port also functioning as exdma controller i/o pins ( edack1 , edack0 , etend1 , etend0 , edreq1 , edreq0 ) ? when dmacs = 1: 6-bit i/o port also functioning as exdma controller i/o pins ( edack1 , edack0 , etend1 , etend0 , edreq1 , edreq0 ) and dma controller i/o pins ( dack1 , dack0 , tend1 , tend0 , dreq1 , dreq0 ) ? when expe = 0 and dmacs = 0 (after reset): 6-bit i/o port ? when expe = 0 and dmacs = 1: 6-bit i/o port also functioning as dma controller i/o pins ( dack1 , dack0 , tend1 , tend0 , dreq1 , dreq0 ) ? when expe = 1 and dmacs = 0: 6-bit i/o port also functioning as exdma controller i/o pins ( edack1 , edack0 , etend1 , etend0 , edreq1 , edreq0 ) ? when expe = 1 and dmacs = 1: 6-bit i/o port also functioning as exdma controller i/o pins ( edack1 , edack0 , etend1 , etend0 , edreq1 , edreq0 ) and dma controller i/o pins ( dack1 , dack0 , tend1 , tend0 , dreq1 , dreq0 )
187 port description pins modes 1, 2, 5, 6 mode 4 mode 7 port 8 ? 6-bit i/o port p85/ edack3 / irq5 p84/ edack2 / irq4 p83/ etend3 / irq3 p82/ etend2 / irq2 p81/ edreq3 / irq1 p80/ edreq2 / irq0 6-bit i/o port also functioning as exdma controller i/o pins ( edack3 , edack2 , etend3 , etend2 , edreq3 , edreq2 ) and interrupt input pins ( irq5 to irq0 ) ? when expe = 0 (after reset): 6-bit i/o port also functioning as interrupt input pins ( irq5 to irq0 ) ? when expe = 1: 6-bit i/o port also functioning as exdma controller i/o pins ( edack3 , edack2 , etend 3, etend 2, edreq 3, edreq2 ) and interrupt input pins ( irq5 to irq0 ) port a ? 8-bit i/o port ? built-in mos input pull-up ? open-drain output capability pa7/a23 pa6/a22 pa5/a21 when a23e to a21e = 1 and ddr = 0 (after reset): input port when a23e to a21e = 0: i/o port when a23e to a21e = 1 and ddr = 1: address output when expe = 0 (after reset), or when expe = 1 and a23e to a16e = 0: i/o port when expe = 1, a23e to a16e = 1, and ddr = 0: input port when expe = 1, a23e to a16e = 1, and ddr = 1: address output pa4/a20?a0/a16 address output when a20e to a16e = 1 and ddr = 0 (after reset): input port when a20e to a16e = 0: i/o port when a20e to a16e = 1 and ddr = 1 (after reset): address output port b ? 8-bit i/o port ? built-in mos input pull-up pb7/a15?b0/a8 address output when ddr = 0 (after reset): input port when ddr = 1: address output when expe = 0 (after reset): i/o port when expe = 1 and ddr = 0 (after reset): input port when expe = 1 and ddr = 1: address output port c ? 8-bit i/o port ? built-in mos input pull-up pc7/a7?c0/a0 address output when ddr = 0 (after reset): input port when ddr = 1: address output when expe = 0 (after reset): i/o port when expe = 1 and ddr = 0: input port when expe = 1 and ddr = 1: address output
188 port description pins modes 1, 2, 5, 6 mode 4 mode 7 port d ? 8-bit i/o port ? built-in mos input pull-up pd7/d15?d0/d8 data bus input/output when expe = 0 (after reset): i/o port when expe = 1: data bus input/output port e ? 8-bit i/o port ? built-in mos input pull-up pe7/d7?e0/d0 in 8-bit bus mode: i/o port in 16-bit bus mode: data bus input/output when expe = 0 (after reset): i/o port when expe = 1 in 8-bit bus mode: i/o port when expe = 1 in 16-bit bus mode: data bus input/output port f ? 8-bit i/o port pf7/ when ddr = 1 (after reset): output when ddr = 0: input port when ddr = 0: input port (after reset) when ddr = 1: ?output pf6/ as when asoe = 1 (after reset): as output when asoe = 0: i/o port when expe = 0 (after reset), or when expe = 1 and asoe = 0: i/o port when expe = 1 and asoe = 1: as output pf5/ rd pf4/ hwr rd , hwr output when expe = 0 (after reset): i/o port when expe = 1: rd , hwr output pf3/ lwr when lwroe = 1 (after reset): lwr output when lwroe = 0: i/o port when expe = 0 (after reset), or when expe = 1 and lwroe = 0: i/o port when expe = 1 and lwroe = 1: lwr output pf2/ lcas / irq15 when areas 2 to 5 are all normal space (after reset), or when dram space areas are all in 8-bit bus mode: i/o port also functioning as irq15 interrupt input when any dram space is in 16-bit bus mode: dual function as irq15 interrupt input and lcas output when expe = 0 (after reset), or when expe = 1 and areas 2 to 5 are all normal space, or when expe = 1 and dram space areas are all in 8-bit bus mode: i/o port also functioning as irq15 interrupt input when expe = 1 and any dram space is in 16-bit bus mode: dual function as irq15 interrupt input and lcas output
189 port description pins modes 1, 2, 5, 6 mode 4 mode 7 port f ? 8-bit i/o port pf1/ ucas / irq14 when areas 2 to 5 are all normal space (after reset): i/o port also functioning as irq14 interrupt input when any of areas 2 to 5 is dram space: dual function as irq14 interrupt input and ucas output when expe = 0 (after reset), or when expe = 1 and areas 2 to 5 are all normal space: i/o port also functioning as irq14 interrupt input when expe = 1 and any of areas 2 to 5 is dram space: dual function as irq14 interrupt input and ucas output pf0/ wait when waite = 0 (after reset): i/o port when waite = 1: wait input when expe = 0 (after reset), or when expe = 1 and waite = 0: i/o port when expe = 1 and waite = 1: wait input port g ? 7-bit i/o port pg6/ breq when brle = 0 (after reset): i/o port when brle = 1: breq input when expe = 0 (after reset), or when expe = 1 and brle = 0: i/o port when expe = 1 and brle = 1: breq input pg5/ back when brle = 0 (after reset): i/o port when brle = 1: back output when expe = 0 (after reset), or when expe = 1 and brle = 0: i/o port when expe = 1 and brle = 1: back output pg4/ breqo when brle = 0 (after reset), or when brle = 1 and breqoe = 0: i/o port when brle = 1 and breqoe = 1: breqo output when expe = 0 (after reset), or when expe1 = 1 and brle = 0, or when expe = 1, brle = 1, and breqoe = 0: i/o port when expe = 1, brle = 1, and breqoe = 1: breqo output pg3/ cs3 when cs3e = 0 (after reset): i/o port when cs3e = 1 and ddr = 0: input port when cs3e = 1 and ddr = 1: cs3 output when expe = 0 (after reset), or when expe1 = 1 and cs3e = 0: i/o port when expe = 1, cs3e = 1, and ddr = 0: input port when expe = 1, cs3e = 1, and ddr = 1: cs3 output
190 port description pins modes 1, 2, 5, 6 mode 4 mode 7 port g ? 7-bit i/o port pg2/ cs2 when cs2e = 0 (after reset): i/o port when cs2e = 1 and ddr = 0: input port when cs2e = 1 and ddr = 1: cs2 output when expe = 0 (after reset), or when expe1 = 1 and cs2e = 0: i/o port when expe = 1, cs2e = 1, and ddr = 0: input port when expe = 1, cs2e = 1, and ddr = 1: cs2 output pg1/ cs1 when cs1e = 0 (after reset): i/o port when cs1e = 1 and ddr = 0: input port when cs1e = 1 and ddr = 1: cs1 output when expe = 0 (after reset), or when expe1 = 1 and cs1e = 0: i/o port when expe = 1, cs1e = 1, and ddr = 0: input port when expe = 1, cs1e = 1, and ddr = 1: cs1 output pg0/ cs0 when cs0e = 1 and ddr = 1 (after reset): cs0 output when cs0e = 0: i/o port when cs0e = 1 and ddr = 0: input port when cs0e = 1 and ddr = 0 (after reset): input port when cs0e = 0: i/o port when cs0e = 1 and ddr = 1: cs0 output when expe = 0 (after reset), or when expe1 = 1 and cs0e = 0: i/o port when expe = 1, cs0e = 1, and ddr = 0: input port when expe = 1, cs0e = 1, and ddr = 1: cs0 output port h ? 4-bit i/o port ph3/ cs7 / oe / irq7 when oee = 0 and cs7e = 0 (after reset), or when oee = 1, oes = 0, and cs7e = 0: i/o port also functioning as irq7 interrupt input when oee = 0, cs7e = 1, and ddr = 0, or when oee = 1, oes = 0, cs7e = 1, and ddr = 0: input port also functioning as irq7 interrupt input when oee = 0, cs7e = 1, and ddr = 1, or when oee = 1, oes = 0, cs7e = 1, and ddr = 1: dual function as irq7 interrupt input and cs7 output when oee = 1 and oes = 1: dual function as irq7 interrupt input and oe output when expe = 0 (after reset), or when expe = 1, oee = 0, and cs7e = 0, or when expe = 1, oee = 1, oes = 0, and cs7e = 0: i/o port also functioning as irq7 interrupt input when expe = 1, oee = 0, cs7e = 1, and ddr = 0, or when expe = 1, oee = 1, oes = 0, cs7e = 1, and ddr = 0: input port also functioning as irq7 interrupt input when expe = 1, oee = 0, cs7e = 1, and ddr = 1, or when oee = 1, oes = 0, cs7e = 1, and ddr = 1: dual function as irq7 interrupt input and cs7 output when expe = 1, oee = 1, and oes = 1: dual function as irq7 interrupt input and oe output
191 port description pins modes 1, 2, 5, 6 mode 4 mode 7 port h ? 4-bit i/o port ph2/ cs6 / irq6 when cs6e = 0 (after reset): i/o port also functioning as irq6 interrupt input when cs6e = 1 and ddr = 0: input port also functioning as irq6 interrupt input when cs6e = 1 and ddr = 1: dual function as irq6 interrupt input and cs6 output when expe = 0 (after reset), or when expe = 1 and cs6e = 0: i/o port also functioning as irq6 interrupt input when expe = 1, cs6e = 1, and ddr = 0: input port also functioning as irq6 interrupt input when expe = 1, cs6e = 1, and ddr = 1: dual function as irq6 interrupt input and cs6 output ph1/ cs5 when cs5e = 0 (after reset): i/o port when cs5e = 1 and ddr = 0: input port when cs5e = 1 and ddr = 1: cs5 output when expe = 0 (after reset), or when expe = 1 and cs5e = 0: i/o port when expe = 1, cs5e = 1, and ddr = 0: input port when expe = 1, cs5e = 1, and ddr = 1: cs5 output ph0/ cs4 when cs4e = 0 (after reset): i/o port when cs4e = 1 and ddr = 0: input port when cs4e = 1 and ddr = 1: cs4 output when expe = 0 (after reset), or when expe = 1 and cs4e = 0: i/o port when expe = 1, cs4e = 1, and ddr = 0: input port when expe = 1, cs4e = 1, and ddr = 1: cs4 output
192 5.2 port 1 5.2.1 overview port 1 is an 8-bit i/o port. port 1 pins also function as ppg output pins (po15 to po8), tpu i/o pins (tclka, tclkb, tclkc, tclkd, tioca0, tiocb0, tiocc0, tiocd0, tioca1, tiocb1, tioca2, and tiocb2), and exdmac output pins ( edrak2 and edrak3 ). the functions of pins p15 to p10 are the same in all operating modes, while the functions of pins p17 and p16 change according to the operating mode. port 1 has schmitt-trigger inputs. figure 5.1 shows the port 1 pin configuration. p17 (i/o) / po15 (output) / tiocb2 (i/o) / tclkd (input) / edrak3 (output) p16 (i/o) / po14 (output) / tioca2 (i/o) / edrak2 (output) p15 (i/o) / po13 (output) / tiocb1 (i/o) / tclkc (input) p14 (i/o) / po12 (output) / tioca1 (i/o) p13 (i/o) / po11 (output) / tiocd0 (i/o) / tclkb (input) p12 (i/o) / po10 (output) / tiocc0 (i/o) / tclka (input) p11 (i/o) / po9 (output) / tiocb0 (i/o) p10 (i/o) / po8 (output) / tioca0 (i/o) modes 1, 2, 4, 5, 6, 7 (expe = 1) p17 (i/o) / po15 (output) / tiocb2 (i/o) / tclkd (input) / edrak3 (output) p16 (i/o) / po14 (output) / tioca2 (i/o) / edrak2 (output) p15 (i/o) / po13 (output) / tiocb1 (i/o) / tclkc (input) p14 (i/o) / po12 (output) / tioca1 (i/o) p13 (i/o) / po11 (output) / tiocd0 (i/o) / tclkb (input) p12 (i/o) / po10 (output) / tiocc0 (i/o) / tclka (input) p11 (i/o) / po9 (output) / tiocb0 (i/o) p10 (i/o) / po8 (output) / tioca0 (i/o) mode 7 (expe = 0) p17 (i/o) / po15 (output) / tiocb2 (i/o) / tclkd (input) p16 (i/o) / po14 (output) / tioca2 (i/o) p15 (i/o) / po13 (output) / tiocb1 (i/o) / tclkc (input) p14 (i/o) / po12 (output) / tioca1 (i/o) p13 (i/o) / po11 (output) / tiocd0 (i/o) / tclkb (input) p12 (i/o) / po10 (output) / tiocc0 (i/o) / tclka (input) p11 (i/o) / po9 (output) / tiocb0 (i/o) p10 (i/o) / po8 (output) / tioca0 (i/o) port 1 port 1 pins figure 5.1 port 1 pin functions
193 5.2.2 register configuration table 5.2 shows the port 1 register configuration. table 5.2 port 1 registers name abbreviation r/w initial value address * port 1 data direction register p1ddr w h'00 h'fe20 port 1 data register p1dr r/w h'00 h'ff60 port 1 register port1 r undefined h'ff50 note: * lower 16 bits of the address. port 1 data direction register (p1ddr) bit 76543210 p17ddr p16ddr p15ddr p14ddr p13ddr p12ddr p11ddr p10ddr initial value 00000000 read/write wwwwwwww p1ddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. p1ddr cannot be read; if it is, an undefined value will be read. setting a p1ddr bit to 1 makes the corresponding port 1 pin an output pin, while clearing the bit to 0 makes the pin an input pin. p1ddr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. port 1 data register (p1dr) bit 76543210 p17dr p16dr p15dr p14dr p13dr p12dr p11dr p10dr initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w p1dr is an 8-bit readable/writable register that stores output data for the port 1 pins (p17 to p10). p1dr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode.
194 port 1 register (port1) bit 76543210 p17 p16 p15 p14 p13 p12 p11 p10 initial value * * * * * * * * read/write rrrrrrrr note: * determined by the state of pins p17 to p10. port1 is an 8-bit read-only register that shows the pin states. port1 cannot be written to; writing of output data for the port 1 pins (p17 to p10) must always be performed on p1dr. if a port 1 read is performed while p1ddr bits are set to 1, the p1dr values are read. if a port 1 read is performed while p1ddr bits are cleared to 0, the pin states are read. after a reset and in hardware standby mode, port1 contents are determined by the pin states, as p1ddr and p1dr are initialized. port1 retains its prior state in software standby mode. 5.2.3 pin functions port 1 pins also function as ppg output pins (po15 to po8), tpu i/o pins (tclka, tclkb, tclkc, tclkd, tioca0, tiocb0, tiocc0, tiocd0, tioca1, tiocb1, tioca2, and tiocb2), and exdmac output pins ( edrak2 and edrak3 ). port 1 pin functions are shown in table 5.3.
195 table 5.3 port 1 pin functions pin selection method and pin functions p17/po15/ tiocb2/ tclkd/ edrak3 the pin function is switched as shown below according to the combination of the tpu channel 2 settings (by bits md3 to md0 in tmdr2, bits iob3 to iob0 in tior2, and bits cclr1 and cclr0 in tcr2), bits tpsc2 to tpsc0 in tcr0 and tcr5, bit nder15 in nderh, bit edrake in edmdr3, and bit p17ddr. modes 1, 2, 4, 5, 6, 7 (expe = 1) edrake 0 1 tpu channel 2 settings (1) in table below (2) in table below p17ddr 011 nder15 01 pin function tiocb2 output p17 input p17 output po15 output edrak3 output tiocb2 input * 1 tclkd input * 2 mode 7 (expe = 0) edrake tpu channel 2 settings (1) in table below (2) in table below p17ddr 011 nder15 01 pin function tiocb2 output p17 input p17 output po15 output tiocb2 input * 1 tclkd input * 2 notes: 1. tiocb2 input when md3 to md0 = b'0000 or b'01xx and iob3 = 1. 2. tclkd input when the setting for either tcr0 or tcr5 is tpsc2 to tpsc0 = b'111. tclkd input when channels 2 and 4 are set to phase counting mode. tpu channel 2 settings (2) (1) (2) (1) (1) (2) md3 to md0 b'0000, b'01xx b'001x b'0010 b'0011 ioa3 to ioa0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr1, cclr0 other than b'10 b'10 output function output compare output pwm * 2 mode 1 output pwm mode 2 output x: don t care
196 pin selection method and pin functions p16/po14/ tioca2/ edrak2 the pin function is switched as shown below according to the combination of the tpu channel 2 settings (by bits md3 to md0 in tmdr2, bits ioa3 to ioa0 in tior2, and bits cclr1 and cclr0 in tcr2), bit nder14 in nderh, bit edrake in edmdr2 and bit p16ddr. modes 1, 2, 4, 5, 6, 7 (expe = 1) edrake 0 1 tpu channel 2 settings (1) in table below (2) in table below p16ddr 011 nder14 01 pin function tioca2 output p16 input p16 output po14 output edrak2 output tioca2 input * 1 mode 7 (expe = 0) edrake tpu channel 2 settings (1) in table below (2) in table below p16ddr 011 nder14 01 pin function tioca2 output p16 input p16 output po14 output tioca2 input * 1 note: 1. tioca2 input when md3 to md0 = b'0000 or b'01xx and ioa3 = 1. tpu channel 2 settings (2) (1) (2) (1) (1) (2) md3 to md0 b'0000, b'01xx b'001x b'0010 b'0011 ioa3 to ioa0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr1, cclr0 other than b'10 b'10 output function output compare output pwm * 2 mode 1 output pwm mode 2 output x: don t care note: 2. tiocb2 output disabled.
197 pin selection method and pin functions p15/po13/ tiocb1/ tclkc the pin function is switched as shown below according to the combination of the tpu channel 1 settings (by bits md3 to md0 in tmdr1, bits iob3 to iob0 in tior1, and bits cclr1 and cclr0 in tcr1), bits tpsc2 to tpsc0 in tcr0, tcr2, tcr4, and tcr5, bit nder13 in nderh, and bit p15ddr. tpu channel 1 settings (1) in table below (2) in table below p15ddr 011 nder13 01 pin function tiocb1 output p15 input p15 output po13 output tiocb1 input * 1 tclkc input * 2 notes: 1. tiocb1 input when md3 to md0 = b'0000 or b'01xx and iob3 to iob0 = b'10xx. 2. tclkc input when the setting for either tcr0 or tcr2 is tpsc2 to tpsc0 = b'110, or when the setting for either tcr4 or tcr5 is tpsc2 to tpsc0 = b'101. tclkc input when phase counting mode is set for channels 2 and 4. tpu channel 1 settings (2) (1) (2) (2) (1) (2) md3 to md0 b'0000, b'01xx b'0010 b'0011 iob3 to iob0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr1, cclr0 other than b'10 b'10 output function output compare output pwm mode 2 output x: don t care
198 pin selection method and pin functions p14/po12/ tioca1 the pin function is switched as shown below according to the combination of the tpu channel 1 settings (by bits md3 to md0 in tmdr1, bits ioa3 to ioa0 in tior1, and bits cclr1 and cclr0 in tcr1), bit nder12 in nderh, and bit p14ddr. tpu channel 1 settings (1) in table below (2) in table below p14ddr 011 nder12 01 pin function tioca1 output p14 input p14 output po12 output tioca1 input * 1 note: 1. tioca1 input when md3 to md0 = b'0000 or b'01xx and ioa3 to ioa0 = b'10xx. tpu channel 1 settings (2) (1) (2) (1) (1) (2) md3 to md0 b'0000, b'01xx b'001x b'0010 b'0011 ioa3 to ioa0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 other than b'xx00 cclr1, cclr0 other than b'01 b'01 output function output compare output pwm * 2 mode 1 output pwm mode 2 output x: don t care note: 2. tiocb1 output disabled.
199 pin selection method and pin functions p13/po11/ tiocd0/ tclkb the pin function is switched as shown below according to the combination of the tpu channel 0 settings (by bits md3 to md0 in tmdr0, bits iod3 to iod0 in tior0l, and bits cclr2 to cclr0 in tcr0), bits tpsc2 to tpsc0 in tcr0 to tcr2, bit nder11 in nderh, and bit p13ddr. tpu channel 0 settings (1) in table below (2) in table below p13ddr 011 nder11 01 pin function tiocd0 output p13 input p13 output po11 output tiocd0 input * 1 tclkb input * 2 notes: 1. tiocd0 input when md3 to md0 = b'0000 and iod3 to iod0 = b'10xx. 2. tclkb input when the setting for any of tcr0 to tcr2 is tpsc2 to tpsc0 = b'101. tclkb input when phase counting mode is set for channels 1 and 5. tpu channel 0 settings (2) (1) (2) (2) (1) (2) md3 to md0 b'0000 b'0010 b'0011 iod3 to iod0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr2, cclr0 other than b'110 b'110 output function output compare output pwm mode 2 output x: don t care
200 pin selection method and pin functions p12/po10/ tiocc0/ tclka the pin function is switched as shown below according to the combination of the tpu channel 0 settings (by bits md3 to md0 in tmdr0, bits ioc3 to ioc0 in tior0l, and bits cclr2 to cclr0 in tcr0), bits tpsc2 to tpsc0 in tcr0 to tcr5, bit nder10 in nderh, and bit p12ddr. tpu channel 0 settings (1) in table below (2) in table below p12ddr 011 nder10 01 pin function tiocc0 output p12 input p12 output po10 output tiocc0 input * 1 tclka input * 2 notes: 1. tiocc0 input when md3 to md0 = b'0000 and ioc3 to ioc0 = b'10xx. 2. tclka input when the setting for any of tcr0 to tcr5 is tpsc2 to tpsc0 = b'100. tclka input when phase counting mode is set for channels 1 and 5. tpu channel 0 settings (2) (1) (2) (1) (1) (2) md3 to md0 b'0000 b'001x b'0010 b'0011 ioc3 to ioc0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 other than b'xx00 cclr2, cclr0 other than b'101 b'101 output function output compare output pwm * 3 mode 1 output pwm mode 2 output x: don t care note: 3. tiocd0 output disabled. output disabled and settings (2) effective when bfa = 1 or bfb = 1 in tmdr0.
201 pin selection method and pin functions p11/po9/ tiocb0 the pin function is switched as shown below according to the combination of the tpu channel 0 settings (by bits md3 to md0 in tmdr0 and bits iob3 to iob0 in tior0h), bit nder9 in nderh, and bit p11ddr. tpu channel 0 settings (1) in table below (2) in table below p11ddr 011 nder9 01 pin function tiocb0 output p11 input p11 output po9 output tiocb0 input * 1 note: 1. tiocb0 input when md3 to md0 = b'0000 and iob3 to iob0 = b'10xx. tpu channel 0 settings (2) (1) (2) (2) (1) (2) md3 to md0 b'0000 b'0010 b'0011 iob3 to iob0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr2, cclr0 other than b'010 b'010 output function output compare output pwm mode 2 output x: don t care
202 pin selection method and pin functions p10/po8/ tioca0 the pin function is switched as shown below according to the combination of the tpu channel 0 settings (by bits md3 to md0 in tmdr0, bits ioa3 to ioa0 in tior0h, and bits cclr2 to cclr0 in tcr0), bit nder8 in nderh, and bit p10ddr. tpu channel 0 settings (1) in table below (2) in table below p10ddr 011 nder8 01 pin function tioca0 output p10 input p10 output po8 output tioca0 input * 1 note: 1. tioca0 input when md3 to md0 = b'0000 and ioa3 to ioa0 = b'10xx. tpu channel 0 settings (2) (1) (2) (1) (1) (2) md3 to md0 b'0000 b'001x b'0010 b'0011 ioa3 to ioa0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 other than b'xx00 cclr2, cclr0 other than b'001 b'001 output function output compare output pwm * 2 mode 1 output pwm mode 2 output x: don t care note: 2. tiocb0 output disabled.
203 5.3 port 2 5.3.1 overview port 2 is an 8-bit i/o port. port 2 pins also function as ppg output pins (po7 to po0), tpu i/o pins (tioca3, tiocb3, tiocc3, tiocd3, tioca4, tiocb4, tioca5, and tiocb5), exdmac output pins ( edrak0 and edrak1 ), and interrupt input pins ( irq15 to irq8 ). the functions of pins p25 to p20 are the same in all operating modes, while the functions of pins p27 and p26 change according to the operating mode. port 2 has schmitt-trigger inputs. figure 5.2 shows the port 2 pin configuration. p27 (i/o) / po7 (output) / tiocb5 (i/o) / edrak1 (output) / irq15 (input) p26 (i/o) / po6 (output) / tioca5 (i/o) / edrak0 (output) / irq14 (input) p25 (i/o) / po5 (output) / tiocb4 (i/o) / irq13 (input) p24 (i/o) / po4 (output) / tioca4 (i/o) / irq12 (input) p23 (i/o) / po3 (output) / tiocd3 (i/o) / irq11 (input) p22 (i/o) / po2 (output) / tiocc3 (i/o) / irq10 (input) p21 (i/o) / po1 (output) / tiocb3 (i/o) / irq9 (input) p20 (i/o) / po0 (output) / tioca3 (i/o) / irq8 (input) modes 1, 2, 4, 5, 6, 7 (expe = 1) p27 (i/o) / po7 (output) / tiocb5 (i/o) / edrak1 (output) / irq15 (input) p26 (i/o) / po6 (output) / tioca5 (i/o) / edrak0 (output) / irq14 (input) p25 (i/o) / po5 (output) / tiocb4 (i/o) / irq13 (input) p24 (i/o) / po4 (output) / tioca4 (i/o) / irq12 (input) p23 (i/o) / po3 (output) / tiocd3 (i/o) / irq11 (input) p22 (i/o) / po2 (output) / tiocc3 (i/o) / irq10 (input) p21 (i/o) / po1 (output) / tiocb3 (i/o) / irq9 (input) p20 (i/o) / po0 (output) / tioca3 (i/o) / irq8 (input) mode 7 (expe = 0) p27 (i/o) / po7 (output) / tiocb5 (i/o) / irq15 (input) p26 (i/o) / po6 (output) / tioca5 (i/o) / irq14 (input) p25 (i/o) / po5 (output) / tiocb4 (i/o) / irq13 (input) p24 (i/o) / po4 (output) / tioca4 (i/o) / irq12 (input) p23 (i/o) / po3 (output) / tiocd3 (i/o) / irq11 (input) p22 (i/o) / po2 (output) / tiocc3 (i/o) / irq10 (input) p21 (i/o) / po1 (output) / tiocb3 (i/o) / irq9 (input) p20 (i/o) / po0 (output) / tioca3 (i/o) / irq8 (input) port 2 port 2 pins figure 5.2 port 2 pin functions
204 5.3.2 register configuration table 5.4 shows the port 2 register configuration. table 5.4 port 2 registers name abbreviation r/w initial value address * port 2 data direction register p2ddr w h'00 h'fe21 port 2 data register p2dr r/w h'00 h'ff61 port 2 register port2 r undefined h'ff51 note: * lower 16 bits of the address. port 2 data direction register (p2ddr) bit 76543210 p27ddr p26ddr p25ddr p24ddr p23ddr p22ddr p21ddr p20ddr initial value 00000000 read/write wwwwwwww p2ddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 2. p2ddr cannot be read; if it is, an undefined value will be read. setting a p2ddr bit to 1 makes the corresponding port 2 pin an output pin, while clearing the bit to 0 makes the pin an input pin. p2ddr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. port 2 data register (p2dr) bit 76543210 p27dr p26dr p25dr p24dr p23dr p22dr p21dr p20dr initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w p2dr is an 8-bit readable/writable register that stores output data for the port 2 pins (p27 to p20). p2dr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode.
205 port 2 register (port2) bit 76543210 p27 p26 p25 p24 p23 p22 p21 p20 initial value * * * * * * * * read/write rrrrrrrr note: * determined by the state of pins p27 to p20. port2 is an 8-bit read-only register that shows the pin states. port2 cannot be written to; writing of output data for the port 2 pins (p27 to p20) must always be performed on p2dr. if a port 2 read is performed while p2ddr bits are set to 1, the p2dr values are read. if a port 2 read is performed while p2ddr bits are cleared to 0, the pin states are read. after a reset and in hardware standby mode, port2 contents are determined by the pin states, as p2ddr and p2dr are initialized. port2 retains its prior state in software standby mode. 5.3.3 pin functions port 2 pins also function as ppg output pins (po7 to po0), tpu i/o pins (tioca3, tiocb3, tiocc3, tiocd3, tioca4, tiocb4, tioca5, and tiocb5), interrupt input pins ( irq15 to irq8 ), and exdmac output pins ( edrak0 and edrak1 ). port 2 pin functions are shown in table 5.5.
206 table 5.5 port 2 pin functions pin selection method and pin functions p27/po7/ tiocb5/ irq15 / edrak1 the pin function is switched as shown below according to the combination of the tpu channel 5 settings (by bits md3 to md0 in tmdr5, bits iob3 to iob0 in tior5, and bits cclr1 and cclr0 in tcr5), bit nder7 in nderl, bit edrake in edmdr1, bit p27ddr, and bit its15 in itsr. modes 1, 2, 4, 5, 6, 7 (expe = 1) edrake 0 1 tpu channel 5 settings (1) in table below (2) in table below p27ddr 011 nder7 01 pin function tiocb5 output p27 input p27 output po7 output edrak1 output tiocb5 input * 1 irq15 interrupt input pin * 2 mode 7 (expe = 0) edrake tpu channel 5 settings (1) in table below (2) in table below p27ddr 011 nder7 01 pin function tiocb5 output p27 input p27 output po7 output tiocb5 input * 1 irq15 interrupt input pin * 2 notes: 1. tiocb5 input when md3 to md0 = b'0000 or b'01xx and iob3 = 1. 2. irq15 input when its15 = 1. tpu channel 5 settings (2) (1) (2) (2) (1) (2) md3 to md0 b'0000 to b'0011 b'0010 b'0011 iob3 to iob0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr1, cclr0 other than b'10 b'10 output function output compare output pwm mode 2 output x: don t care
207 pin selection method and pin functions p26/po6/ tioca5/ irq14 / edrak0 the pin function is switched as shown below according to the combination of the tpu channel 5 settings (by bits md3 to md0 in tmdr5, bits ioa3 to ioa0 in tior5, and bits cclr1 and cclr0 in tcr5), bit nder6 in nderl, bit edrake in edmdr0, bit p26ddr, and bit its14 in itsr. modes 1, 2, 4, 5, 6, 7 (expe = 1) edrake 0 1 tpu channel 5 settings (1) in table below (2) in table below p26ddr 011 nder6 01 pin function tioca5 output p26 input p26 output po6 output edrak0 output tioca5 input * 1 irq14 interrupt input pin * 2 mode 7 (expe = 0) edrake tpu channel 5 settings (1) in table below (2) in table below p26ddr 011 nder6 01 pin function tioca5 output p26 input p26 output po6 output tioca5 input * 1 irq14 interrupt input pin * 2 notes: 1. tioca5 input when md3 to md0 = b'0000 or b'01xx and ioa3 = 1. 2. irq14 input when its14 = 1. tpu channel 5 settings (2) (1) (2) (2) (1) (2) md3 to md0 b'0000 to b'0011 b'0010 b'0010 b'0011 ioa3 to ioa0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 other than b'xx00 cclr1, cclr0 other than b'10 b'10 output function output compare output pwm * 3 mode 1 output pwm mode 2 output x: don t care note: 3. tiocb5 output disabled.
208 pin selection method and pin functions p25/po5/ tiocb4/ irq13 the pin function is switched as shown below according to the combination of the tpu channel 4 settings (by bits md3 to md0 in tmdr4, bits iob3 to iob0 in tior4, and bits cclr1 and cclr0 in tcr4), bit nder5 in nderl, bit p25ddr, and bit its13 in itsr. tpu channel 4 settings (1) in table below (2) in table below p25ddr 011 nder5 01 pin function tiocb4 output p25 input p25 output po5 output tiocb4 input * 1 irq13 interrupt input pin * 2 notes: 1. tiocb4 input when md3 to md0 = b'0000 or b'01xx and iob3 to iob0 = b'10xx. 2. irq13 input when its13 = 1. tpu channel 5 settings (2) (1) (2) (2) (1) (2) md3 to md0 b'0000 to b'0011 b'0010 b'0011 iob3 to iob0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr1, cclr0 other than b'10 b'10 output function output compare output pwm mode 2 output x: don t care
209 pin selection method and pin functions p24/po4/ tioca4/ irq12 the pin function is switched as shown below according to the combination of the tpu channel 4 settings (by bits md3 to md0 in tmdr4 and bits ioa3 to ioa0 in tior4), bit nder4 in nderl, bit p24ddr, and bit its12 in itsr. tpu channel 4 settings (1) in table below (2) in table below p24ddr 011 nder4 01 pin function tioca4 output p24 input p24 output po4 output tioca4 input * 1 irq12 interrupt input pin * 2 notes: 1. tioca4 input when md3 to md0 = b'0000 or b'01xx and ioa3 to ioa0 = b'10xx. 2. irq12 input when its12 = 1. tpu channel 4 settings (2) (1) (2) (1) (1) (2) md3 to md0 b'0001 to b'01xx b'001x b'0010 b'0011 ioa3 to ioa0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 other than b'xx00 cclr1, cclr0 other than b'10 b'10 output function output compare output pwm * 3 mode 1 output pwm mode 2 output x: don t care note: 3. tiocb4 output disabled.
210 pin selection method and pin functions p23/po3/ tiocd3/ irq11 the pin function is switched as shown below according to the combination of the tpu channel 3 settings (by bits md3 to md0 in tmdr3, bits iod3 to iod0 in tior3l, and bits cclr2 to cclr0 in tcr3), bit nder3 in nderl, bit p23ddr, and bit its11 in itsr. tpu channel 3 settings (1) in table below (2) in table below p23ddr 011 nder3 01 pin function tiocd3 output p23 input p23 output po3 output tiocd3 input * 1 irq11 interrupt input pin * 2 notes: 1. tiocd3 input when md3 to md0 = b'0000 and iod3 to iod0 = b'10xx. 2. irq11 input when its11 = 1. tpu channel 3 settings (2) (1) (2) (2) (1) (2) md3 to md0 b'0001 to b'0011 b'0010 b'0011 iod3 to iod0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr2 to cclr0 other than b'110 b'110 output function output compare output pwm mode 2 output x: don t care
211 pin selection method and pin functions p22/po2/ tiocc3/ irq10 the pin function is switched as shown below according to the combination of the tpu channel 3 settings (by bits md3 to md0 in tmdr3, bits ioc3 to ioc0 in tior3l, and bits cclr2 to cclr0 in tcr3), bit nder2 in nderl, bit p22ddr, and bit its10 in itsr. tpu channel 3 settings (1) in table below (2) in table below p22ddr 011 nder2 01 pin function tiocc3 output p22 input p22 output po2 output tiocc3 input * 1 irq10 interrupt input pin * 2 notes: 1. tiocc3 input when md3 to md0 = b'0000 and ioc3 to ioc0 = b'10xx. 2. irq10 input when its10 = 1. tpu channel 3 settings (2) (1) (2) (1) (1) (2) md3 to md0 b'0001 to b'01xx b'001x b'0010 b'0011 ioc3 to ioc0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 other than b'xx00 cclr2 to cclr0 other than b'101 b'101 output function output compare output pwm * 3 mode 1 output pwm mode 2 output x: don t care note: 3. tiocd3 output disabled. output disabled and settings (2) effective when bfa = 1 or bfb = 1 in tmdr3.
212 pin selection method and pin functions p21/po1/ tiocb3/ irq9 the pin function is switched as shown below according to the combination of the tpu channel 3 settings (by bits md3 to md0 in tmdr3, bits iob3 to iob0 in tior3h, and bits cclr2 to cclr0 in tcr3), bit nder1 in nderl, bit p21ddr, and bit its9 in itsr. tpu channel 3 settings (1) in table below (2) in table below p21ddr 011 nder1 01 pin function tiocb3 output p21 input p21 output po1 output tiocb3 input * 1 irq9 interrupt input pin * 2 notes: 1. tiocb3 input when md3 to md0 = b'0000 and iob3 to iob0 = b'10xx. 2. irq9 input when its9 = 1. tpu channel 3 settings (2) (1) (2) (2) (1) (2) md3 to md0 b'0001 to b'0011 b'0010 b'0011 iob3 to iob0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr2 to cclr0 other than b'010 b'010 output function output compare output pwm mode 2 output x: don t care
213 pin selection method and pin functions p20/po0/ tioca3/ irq8 the pin function is switched as shown below according to the combination of the tpu channel 3 settings (by bits md3 to md0 in tmdr3, bits ioa3 to ioa0 in tior3h, and bits cclr2 to cclr0 in tcr3), bit nder0 in nderl, bit p20ddr, and bit its8 in itsr. tpu channel 3 settings (1) in table below (2) in table below p20ddr 011 nder0 01 pin function tioca3 output p20 input p20 output po0 output tioca3 input * 1 irq8 interrupt input pin * 2 notes: 1. tioca3 input when md3 to md0 = b'0000 and ioa3 to ioa0 = b'10xx. 2. irq8 input when its8 = 1. tpu channel 3 settings (2) (1) (2) (1) (1) (2) md3 to md0 b'0001 to b'01xx b'001x b'0010 b'0011 ioa3 to ioa0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 other than b'xx00 cclr2 to cclr0 other than b'001 b'001 output function output compare output pwm * 3 mode 1 output pwm mode 2 output x: don t care note: 3. tiocb3 output disabled.
214 5.4 port 3 5.4.1 overview port 3 is a 6-bit i/o port. port 3 pins also function as sci input/output pins (txd0/irtxd, rxd0/irrxd, sck0, txd1, rxd1, and sck1), and a bus control signal output pin ( oe ). the functions of pins p34 to p30 are the same in all operating modes, while the function of pin p35 changes according to the operating mode. figure 5.3 shows the port 3 pin configuration. p35 (i/o) / sck1 (i/o) / oe (output) p34 (i/o) / sck0 (i/o) p33 (i/o) / rxd1 (input) p32 (i/o) / rxd0/irrxd (input) p31 (i/o) / txd1 (output) p30 (i/o) / txd0/irtxd (output) modes 1, 2, 4, 5, 6, 7 (expe = 1) p35 (i/o) / sck1 (i/o) / oe (output) p34 (i/o) / sck0 (i/o) p33 (i/o) / rxd1 (input) p32 (i/o) / rxd0/irrxd (input) p31 (i/o) / txd1 (output) p30 (i/o) / txd0/irtxd (output) mode 7 (expe = 0) p35 (i/o) / sck1 (i/o) p34 (i/o) / sck0 (i/o) p33 (i/o) / rxd1 (input) p32 (i/o) / rxd0/irrxd (input) p31 (i/o) / txd1 (output) p30 (i/o) / txd0/irtxd (output) port 3 port 3 pins figure 5.3 port 3 pin functions
215 5.4.2 register configuration table 5.6 shows the port 3 register configuration. table 5.6 port 3 registers name abbreviation r/w initial value * 2 address * 1 port 3 data direction register p3ddr w h'00 h'fe22 port 3 data register p3dr r/w h'00 h'ff62 port 3 register port3 r undefined h'ff52 port 3 open drain control register p3odr r/w h'00 h'fe3c port function control register 2 pfcr2 r/w h'0e h'fe34 notes: 1. lower 16 bits of the address. 2. value of bits 5 to 0. port 3 data direction register (p3ddr) bit 76543210 p35ddr p34ddr p33ddr p32ddr p31ddr p30ddr initial value 00000000 read/write wwwwww p3ddr is a 6-bit write-only register, the individual bits of which specify input or output for the pins of port 3. p3ddr cannot be read; if it is, an undefined value will be read. bits 7 and 6 are reserved. setting a p3ddr bit to 1 makes the corresponding port 3 pin an output pin, while clearing the bit to 0 makes the pin an input pin. p3ddr is initialized to h'00 (bits 5 to 0) by a reset and in hardware standby mode. it retains its prior state in software standby mode. as the sci is initialized, the pin states are determined by the p3ddr and p3dr specifications.
216 port 3 data register (p3dr) bit 76543210 p35dr p34dr p33dr p32dr p31dr p30dr initial value 00000000 read/write r/w r/w r/w r/w r/w r/w p3dr is a 6-bit readable/writable register that stores output data for the port 3 pins (p35 to p30). bits 7 and 6 are reserved; they are always read as 0 and cannot be modified. p3dr is initialized to h'00 (bits 5 to 0) by a reset and in hardware standby mode. it retains its prior state in software standby mode. port 3 register (port3) bit 76543210 p35 p34 p33 p32 p31 p30 initial value undefined undefined * * * * * * read/write rrrrrr note: * determined by the state of pins p35 to p30. port3 is a 6-bit read-only register that shows the pin states. port3 cannot be written to; writing of output data for the port 3 pins (p35 to p30) must always be performed on p3dr. bits 7 and 6 are reserved; if read they will return an undefined value. if a port 3 read is performed while p3ddr bits are set to 1, the p3dr values are read. if a port 3 read is performed while p3ddr bits are cleared to 0, the pin states are read. after a reset and in hardware standby mode, port3 contents are determined by the pin states, as p3ddr and p3dr are initialized. port3 retains its prior state in software standby mode. port 3 open drain control register (p3odr) bit 76543210 p35odr p34odr p33odr p32odr p31odr p30odr initial value 00000000 read/write r/w r/w r/w r/w r/w r/w
217 p3odr is a 6-bit readable/writable register that controls the pmos on/off status for each port 3 pin (p35 to p30). bits 7 and 6 are reserved; they are always read as 0 and cannot be modified. setting a p3odr bit to 1 makes the corresponding port 3 pin an nmos open-drain output pin, while clearing the bit to 0 makes the pin a cmos output pin. p3odr is initialized to h'00 (bits 5 to 0) by a reset and in hardware standby mode. it retains its prior state in software standby mode. port function control register 2 (pfcr2) bit 76543210 asoe lwroe oes dmacs initial value 00001110 read/write r/w r/w r/w r/w pfcr2 is an 8-bit readable/writable register that performs i/o port control. pfcr2 is initialized to h'0e by a reset and in hardware standby mode. it retains its prior state in software standby mode. bits 7 to 4?eserved: these bits are always read as 0, and should only be written with 0. bit 1?e output select (oes): selects the oe output pin port when the oee bit is set to 1 in dramcr (enabling oe output). bit 1 oes description 0 p35 is designated as oe output pin 1 ph3 is designated as oe output pin (initial value) 5.4.3 pin functions port 3 pins also function as sci input/output pins (txd0/irtxd, rxd0/irrxd, sck0, txd1, rxd1, and sck1), and a bus control signal output pin ( oe ). port 3 pin functions are shown in table 5.7.
218 table 5.7 port 3 pin functions pin selection method and pin functions p35/sck1/ oe the pin function is switched as shown below according to the combination of the c/ a bit in smr of sci1, bits cke0 and cke1 and rmts2 to rmts0 in scr, bit oes in pfcr2, and bit p35ddr. modes 1, 2, 4, 5, 6, 7 (expe = 1) oee 0 1 oes 10 cke1 0 1 0 1 c/ a 01 01 cke0 0 1 01 p35ddr 0 1 01 pin function p35 input pin p35 output pin * sck1 output pin * sck1 output pin * sck1 input pin p35 input pin p35 output pin * sck1 output pin * sck1 output pin * sck1 input pin oe output mode 7 (expe = 0) oee oes cke1 0 c/ a 01 cke0 0 1 p35ddr 0 1 pin function p35 input pin p35 output pin * sck1 output pin * sck1 output pin * sck1 input pin note: * nmos open-drain output when p35odr = 1. p34/sck0 the pin function is switched as shown below according to the combination of bit c/ a in smr of sci0, bits cke0 and cke1 in scr, and bit p34ddr. cke1 0 1 c/ a 01 cke0 0 1 p34ddr 0 1 pin function p34 input pin p34 output pin * sck0 output pin * sck0 output pin * sck0 input pin note: * nmos open-drain output when p34odr = 1.
219 pin selection method and pin functions p33/rxd1 the pin function is switched as shown below according to the combination of bit re in scr of sci1 and bit p33ddr. re 0 1 p33ddr 0 1 pin function p33 input pin p33 output pin * rxd1 input pin note: * nmos open-drain output when p33odr = 1. p32/rxd0/ irrxd the pin function is switched as shown below according to the combination of bit re in scr of sci0 and bit p32ddr. re 0 1 p32ddr 0 1 pin function p32 input pin p32 output pin * rxd0/irrxd input pin note: * nmos open-drain output when p32odr = 1. p31/txd1 the pin function is switched as shown below according to the combination of bit te in scr of sci1 and bit p31ddr. te 0 1 p31ddr 0 1 pin function p31 input pin p31 output pin * txd1 output pin * note: * nmos open-drain output when p31odr = 1. p30/txd0/ irtxd the pin function is switched as shown below according to the combination of bit te in scr of sci0 and bit p30ddr. te 0 1 p30ddr 0 1 pin function p30 input pin p30 output pin * txd0/irtxd output pin * note: * nmos open-drain output when p30odr = 1.
220 5.5 port 4 5.5.1 overview port 4 is an 8-bit input-only port. port 4 pins also function as a/d converter analog input pins (an0 to an7) and d/a converter analog output pins (da0 and da1). port 4 pin functions are the same in all operating modes. figure 5.4 shows the port 4 pin configuration. p47 (input) / an7 (input) / da1 (output) p46 (input) / an6 (input) / da0 (output) p45 (input) / an5 (input) p44 (input) / an4 (input) p43 (input) / an3 (input) p42 (input) / an2 (input) p41 (input) / an1 (input) p40 (input) / an0 (input) port 4 port 4 pins figure 5.4 port 4 pin functions 5.5.2 register configuration table 5.8 shows the port 4 register configuration. port 4 is an input-only register, and does not have a data direction register or data register. table 5.8 port 4 register name abbreviation r/w initial value address * port 4 register port4 r undefined h'ff53 note: * lower 16 bits of the address.
221 port 4 register (port4) the pin states are always read when a port 4 read is performed. bit 76543210 p47 p46 p45 p44 p43 p42 p41 p40 initial value * * * * * * * * read/write rrrrrrrr note: * determined by the state of pins p47 to p40. 5.5.3 pin functions port 4 pins also function as a/d converter analog input pins (an0 to an7) and d/a converter analog output pins (da0 and da1).
222 5.6 port 5 5.6.1 overview port 5 comprises a 4-bit i/o port (p53 to p50) and a 4-bit input-only port (p57 to p54). port 5 pins also function as sci input/output pins (txd2, rxd2, and sck2), the a/d converter input pin ( adtrg ), a/d converter analog input pins (an12 to an15), d/a converter analog output pins (da2 and da3), and interrupt input pins ( irq7 to irq0 ). port 5 pin functions are the same in all operating modes. figure 5.5 shows the port 5 pin configuration. p57 (input) / an15 (input) / da3 (output) / irq7 (input) p56 (input) / an14 (input) / da2 (output) / irq6 (input) p55 (input) / an13 (input) / irq5 (input) p54 (input) / an12 (input) / irq4 (input) p53 (i/o) / adtrg (input) / irq3 (input) p52 (i/o) / sck2 (i/o) / irq2 (input) p51 (i/o) / rxd2 (input) / irq1 (input) p50 (i/o) / txd2 (output) / irq0 (input) port 5 port 5 pins figure 5.5 port 5 pin functions 5.6.2 register configuration table 5.9 shows the port 5 register configuration. bits 7 to 4 of port 5 are input-only ports, and do not have corresponding data direction register or data register bits. table 5.9 port 5 registers name abbreviation r/w initial value address * port 5 data direction register p5ddr w h'0 0 h'fe24 port 5 data register p5dr r/w h'0 0 h'ff64 port 5 register port5 r undefined h'ff54 note: * lower 16 bits of the address.
223 port 5 data direction register (p5ddr) bit 76543210 p53ddr p52ddr p51ddr p50ddr initial value 00000000 read/write wwww p5ddr is a 4-bit write-only register, the individual bits of which specify input or output for the pins of port 5. p5ddr cannot be read; if it is, an undefined value will be read. bits 7 to 4 are reserved. setting a p5ddr bit to 1 makes the corresponding port 5 pin an output pin, while clearing the bit to 0 makes the pin an input pin. p5ddr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. as the sci is initialized, the pin states are determined by the p5ddr and p5dr specifications. port 5 data register (p5dr) bit 76543210 p53dr p52dr p51dr p50dr initial value 00000000 read/write r/w r/w r/w r/w p5dr is a 4-bit readable/writable register that stores output data for the port 5 pins (p53 to p50). bits 7 to 4 are reserved; they are always read as 0 and cannot be modified. p5dr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. port 5 register (port5) bit 76543210 p57 p56 p55 p54 p53 p52 p51 p50 initial value * * * * * * * * read/write rrrrrrrr note: * determined by the state of pins p57 to p50.
224 port5 is an 8-bit read-only register that shows the pin states. port5 cannot be written to; writing of output data for the port 5 pins (p53 to p50) must always be performed on p5dr. when a port 5 read is performed, the pin states are always read from bits 7 to 4 regardless of the p5ddr settings. if a port 5 read is performed while p5ddr bits are set to 1, the p5dr values are read. if a port 5 read is performed while p5ddr bits are cleared to 0, the pin states are read. after a reset and in hardware standby mode, port5 contents are determined by the pin states, as p5ddr and p5dr are initialized. port5 retains its prior state in software standby mode. 5.6.3 pin functions port 5 pins also function as sci input/output pins (txd2, rxd2, and sck2), the a/d converter input pin ( adtrg ), a/d converter analog input pins (an15 to an12), d/a converter analog output pins (da3 and da2), and interrupt input pins ( irq7 to irq0 ). port 5 pin functions are shown in table 5.10.
225 table 5.10 port 5 pin functions pin selection method and pin functions p57/an15/ da3/ irq7 the pin function is switched as shown below according to bit its7 in itsr. pin function irq7 interrupt input pin * an15 input da3 output note: * irq7 input when its7 = 0. p56/an14/ da2/ irq6 the pin function is switched as shown below according to bit its6 in itsr. pin function irq6 interrupt input pin * an14 input da2 output note: * irq6 input when its6 = 0. p55/an13/ irq5 the pin function is switched as shown below according to bit its5 in itsr. pin function irq5 interrupt input pin * an13 input note: * irq5 input when its5 = 0. p54/an12/ irq4 the pin function is switched as shown below according to bit its4 in itsr. pin function irq4 interrupt input pin * an12 input note: * irq4 input when its4 = 0. p53/ adtrg / irq3 the pin function is switched as shown below according to the combination of bits trgs1 and trgs0 in the a/d control register (adcr), bit its3 in itsr, and bit p53ddr. p53ddr 0 1 pin function p53 input pin p53 output pin adtrg input pin * 1 irq3 interrupt input pin * 2 notes: 1. adtrg input when trgs1 = trgs0 = 0. 2. irq3 input when its3 = 0.
226 pin selection method and pin functions p52/sck2/ irq2 the pin function is switched as shown below according to the combination of bit c/ a in smr of sci2, bits cke0 and cke1 in scr, bit its2 in itsr, and bit p52ddr. cke1 0 1 c/ a 01 cke0 0 1 p52ddr 0 1 pin function p52 input pin p52 output pin sck2 output pin sck2 output pin sck2 input pin irq2 interrupt input pin * note: * irq2 input when its2 = 0. p51/rxd2/ irq1 the pin function is switched as shown below according to the combination of bit re in scr of sci2, bit its1 in itsr, and bit p51ddr. re 0 1 p51ddr 0 1 pin function p51 input pin p51 output pin rxd2 input pin irq1 interrupt input pin * note: * irq1 input when its1 = 0. p50/txd2/ irq0 the pin function is switched as shown below according to the combination of bit te in scr of sci2, bit its0 in itsr, and bit p50ddr. te 0 1 p50ddr 0 1 pin function p50 input pin p50 output pin txd2 input pin irq0 interrupt input pin * note: * irq0 input when its0 = 0.
227 5.7 port 6 5.7.1 overview port 6 is a 6-bit i/o port. port 6 pins also function as 8-bit timer input/output pins (tmri0, tmci0, tmo0, tmri1, tmci1, and tmo1), interrupt input pins ( irq13 to irq8 ), and dmac input/output pins ( dreq0 , tend0 , dack0 , dreq1 , tend1 , and dack1 ). port 6 pin functions are the same in all operating modes. dmac input/output pins can be switched to port 7 by setting the dmacs bit in pfcr2. when pins p65 to p60 are used for irq input, they are schmitt-trigger inputs. figure 5.6 shows the port 6 pin configuration. p65 (i/o) / tmo1 (output) / dack1 (output) / irq13 (input) p64 (i/o) / tmo0 (output) / dack0 (output) / irq12 (input) p63 (i/o) / tmci1 (input) / tend1 (output) / irq11 (input) p62 (i/o) / tmci0 (input) / tend0 (output) / irq10 (input) p61 (i/o) / tmri1 (input) / dreq1 (input) / irq9 (input) p60 (i/o) / tmri0 (input) / dreq0 (input) / irq8 (input) port 6 port 6 pins figure 5.6 port 6 pin functions 5.7.2 register configuration table 5.11 shows the port 6 register configuration. table 5.11 port 6 registers name abbreviation r/w initial value address * port 6 data direction register p6ddr w h'00 h'fe25 port 6 data register p6dr r/w h'00 h'ff65 port 6 register port6 r undefined h'ff55 port function control register 2 pfcr2 r/w h'0e h'fe34 note: * lower 16 bits of the address.
228 port 6 data direction register (p6ddr) bit 76543210 p65ddr p64ddr p63ddr p62ddr p61ddr p60ddr initial value 00000000 read/write wwwwww p6ddr is a 6-bit write-only register, the individual bits of which specify input or output for the pins of port 6. p6ddr cannot be read; if it is, an undefined value will be read. bits 7 and 6 are reserved. setting a p6ddr bit to 1 makes the corresponding port 6 pin an output pin, while clearing the bit to 0 makes the pin an input pin. p6ddr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. port 6 data register (p6dr) bit 76543210 p65dr p64dr p63dr p62dr p61dr p60dr initial value 00000000 read/write r/w r/w r/w r/w r/w r/w p6dr is a 6-bit readable/writable register that stores output data for the port 6 pins (p65 to p60). bits 7 and 6 are reserved; they are always read as 0 and cannot be modified. p6dr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. port 6 register (port6) bit 76543210 p65 p64 p63 p62 p61 p60 initial value undefined undefined * * * * * * read/write rrrrrr note: * determined by the state of pins p65 to p60. port6 is a 6-bit read-only register that shows the pin states. port6 cannot be written to; writing of output data for the port 6 pins (p65 to p60) must always be performed on p6dr.
229 bits 7 and 6 are reserved; if read they will return an undefined value. if a port 6 read is performed while p6ddr bits are set to 1, the p6dr values are read. if a port 6 read is performed while p6ddr bits are cleared to 0, the pin states are read. after a reset and in hardware standby mode, port6 contents are determined by the pin states, as p6ddr and p6dr are initialized. port6 retains its prior state in software standby mode. port function control register 2 (pfcr2) bit 76543210 asoe lwroe oes dmacs initial value 00001110 read/write r/w r/w r/w r/w pfcr2 is an 8-bit readable/writable register that performs i/o port control. pfcr2 is initialized to h'0e by a reset and in hardware standby mode. it retains its prior state in software standby mode. bits 7 to 4?eserved: these bits are always read as 0, and should only be written with 0. bit 0?mac control pin select (dmacs): selects the dmac control port. bit 0 dmacs description 0 p65 to p60 are designated as dmac control pins (initial value) 1 p75 to p70 are designated as dmac control pins 5.7.3 pin functions port 6 pins also function as 8-bit timer input/output pins (tmri0, tmci0, tmo0, tmri1, tmci1, and tmo1), interrupt input pins ( irq13 to irq8 ), and dmac input/output pins ( dreq0 , tend0 , dack0 , dreq1 , tend1 , and dack1 ). port 6 pin functions are shown in table 5.12.
230 table 5.12 port 6 pin functions pin selection method and pin functions p65/tmo1/ dack1 / irq13 the pin function is switched as shown below according to the combination of bit dmacs in pfcr2, bit sae1 in dmabcrh, bits os3 to os0 in tcsr1 of the 8- bit timer, bit p65ddr, and bit its13 in itsr. sae1 0 1 dmacs 10 os3 to os0 all 0 not all 0 all 0 not all 0 p65ddr 0 1 01 pin function p65 input pin p65 output pin tmo1 output pin p65 input pin p65 output pin tmo1 output pin dack1 output pin irq13 interrupt input pin * note: * irq13 interrupt input when its13 = 0. p64/tmo0/ dack0 / irq12 the pin function is switched as shown below according to the combination of bit dmacs in pfcr2, bit sae1 in dmabcrh, bits os3 to os0 in tcsr1 of the 8- bit timer, bit p64ddr, and bit its12 in itsr. sae0 0 1 dmacs 10 os3 to os0 all 0 not all 0 all 0 not all 0 p64ddr 0 1 01 pin function p64 input pin p64 output pin tmo0 output pin p64 input pin p64 output pin tmo0 output pin dack0 output pin irq12 interrupt input pin * note: * irq12 interrupt input when its12 = 0.
231 pin selection method and pin functions p63/tmci1/ tend1 / irq11 the pin function is switched as shown below according to the combination of bit dmacs in pfcr2, bit tee1 in dmatcr of the dmac, bit p63ddr, and bit its11 in itsr. tee1 0 1 dmacs 10 p63ddr 0101 pin function p63 input pin p63 output pin p63 input pin p63 output pin tend1 output pin irq11 interrupt input pin * note: * irq11 interrupt input when its11 = 0. p62/tmci0/ tend0 / irq10 the pin function is switched as shown below according to the combination of bit dmacs in pfcr2, bit tee0 in dmatcr of the dmac, bit p62ddr, and bit its10 in itsr. tee0 0 1 dmacs 10 p62ddr 0101 pin function p62 input pin p62 output pin p62 input pin p62 output pin tend0 output pin irq10 interrupt input pin * note: * irq10 interrupt input when its10 = 0. p61/tmri1/ dreq1 / irq9 the pin function is switched as shown below according to the combination of bit p61ddr and bit its9 in itsr. p61ddr 0 1 pin function p61 input pin p61 output pin tmri1 input pin dreq1 input pin * 1 irq9 interrupt input pin * 2 notes: 1. dreq1 input when dmaks = 0. 2. irq9 interrupt input when its9 = 0.
232 pin selection method and pin functions p60/tmri0/ dreq0 / irq8 the pin function is switched as shown below according to the combination of bit p60ddr and bit its8 in itsr. p60ddr 0 1 pin function p60 input pin p60 output pin tmri0 input pin dreq0 input pin * 1 irq8 interrupt input pin * 2 notes: 1. dreq0 input when dmaks = 0. 2. irq8 interrupt input when its8 = 0.
233 5.8 port 7 5.8.1 overview port 7 is a 6-bit i/o port. port 7 pins also function as dmac input/output pins ( dreq0 , tend0 , dack0 , dreq1 , tend1 , and dack1 ) and exdmac input/output pins ( edreq0 , etend0 , edack0 , edreq1 , etend1 , and edack1 ). the functions of pins p75 to p70 change according to the operating mode. dmac input/output pins can be switched to port 6 by setting the dmacs bit in pfcr2. figure 5.7 shows the port 7 pin configuration. p75 (i/o) / dack1 (output) / edack1 (output) p74 (i/o) / dack0 (output) / edack0 (output) p73 (i/o) / tend1 (output) / etend1 (output) p72 (i/o) / tend0 (output) / etend0 (output) p71 (i/o) / dreq1 (input) / edreq1 (input) p70 (i/o) / dreq0 (input) / edreq0 (input) modes 1, 2, 4, 5, 6, 7 (expe = 1) p75 (i/o) / dack1 (output) / edack1 (output) p74 (i/o) / dack0 (output) / edack0 (output) p73 (i/o) / tend1 (output) / etend1 (output) p72 (i/o) / tend0 (output) / etend0 (output) p71 (i/o) / dreq1 (input) / edreq1 (input) p70 (i/o) / dreq0 (input) / edreq0 (input) mode 7 (expe = 0) p75 (i/o) / dack1 (output) p74 (i/o) / dack0 (output) p73 (i/o) / tend1 (output) p72 (i/o) / tend0 (output) p71 (i/o) / dreq1 (input) p70 (i/o) / dreq0 (input) port 7 port 7 pins figure 5.7 port 7 pin functions
234 5.8.2 register configuration table 5.13 shows the port 7 register configuration. table 5.13 port 7 registers name abbreviation r/w initial value address * 1 port 7 data direction register p7ddr w h'00 * 2 h'fe26 port 7 data register p7dr r/w h'00 * 2 h'ff66 port 7 register port7 r undefined h'ff56 port function control register 2 pfcr2 r/w h'0e h'fe34 notes: 1. lower 16 bits of the address. 2. value of bits 5 to 0. port 7 data direction register (p7ddr) bit 76543210 p75ddr p74ddr p73ddr p72ddr p71ddr p70ddr initial value 00000000 read/write wwwwww p7ddr is a 6-bit write-only register, the individual bits of which specify input or output for the pins of port 7. p7ddr cannot be read; if it is, an undefined value will be read. bits 7 and 6 are reserved. setting a p7ddr bit to 1 makes the corresponding port 7 pin an output pin, while clearing the bit to 0 makes the pin an input pin. p7ddr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. port 7 data register (p7dr) bit 76543210 p75dr p74dr p73dr p72dr p71dr p70dr initial value 00000000 read/write r/w r/w r/w r/w r/w r/w p7dr is a 6-bit readable/writable register that stores output data for the port 7 pins (p75 to p70). bits 7 and 6 are reserved; they are always read as 0 and cannot be modified.
235 p7dr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. port 7 register (port7) bit 76543210 p75 p74 p73 p72 p71 p70 initial value undefined undefined * * * * * * read/write rrrrrr note: * determined by the state of pins p75 to p70. port7 is a 6-bit read-only register that shows the pin states. port7 cannot be written to; writing of output data for the port 7 pins (p75 to p70) must always be performed on p7dr. bits 7 and 6 are reserved; if read they will return an undefined value. if a port 7 read is performed while p7ddr bits are set to 1, the p7dr values are read. if a port 7 read is performed while p7ddr bits are cleared to 0, the pin states are read. after a reset and in hardware standby mode, port7 contents are determined by the pin states, as p7ddr and p7dr are initialized. port7 retains its prior state in software standby mode. port function control register 2 (pfcr2) bit 76543210 asoe lwroe oes dmacs initial value 00001110 read/write r/w r/w r/w r/w pfcr2 is an 8-bit readable/writable register that performs i/o port control. pfcr2 is initialized to h'0e by a reset and in hardware standby mode. it retains its prior state in software standby mode. bits 7 to 4?eserved: these bits are always read as 0, and should only be written with 0. bit 0?mac control pin select (dmacs): selects the dmac control port. bit 0 dmacs description 0 p65 to p60 are designated as dmac control pins (initial value) 1 p75 to p70 are designated as dmac control pins
236 5.8.3 pin functions port 7 pins also function as dmac input/output pins ( dreq0 , tend0 , dack0 , dreq1 , tend1 , and dack1 ) and exdmac input/output pins ( edreq0 , etend0 , edack0 , edreq1 , etend1 , and edack1 ). port 7 pin functions are shown in table 5.14. table 5.14 port 7 pin functions pin selection method and pin functions p75/ dack1 / edack1 the pin function is switched as shown below according to the combination of bit dmacs in pfcr2, bit sae1 in dmabcrh, bit ams in edmdr1, and bit p75ddr. modes 1, 2, 4, 5, 6, 7 (expe = 1) ams 0 1 sae1 0 1 dmacs 01 p75ddr 0 1 0 1 pin function p75 input pin p75 output pin p75 input pin p75 output pin dack1 output pin edack1 output pin mode 7 (expe = 0) ams sae1 0 1 dmacs 01 p75ddr 0101 pin function p75 input pin p75 output pin p75 input pin p75 output pin dack1 output pin
237 pin selection method and pin functions p74/ dack0 / edack0 the pin function is switched as shown below according to the combination of bit dmacs in pfcr2, bit sae0 in dmabcrh, bit ams in edmdr0, and bit p74ddr. modes 1, 2, 4, 5, 6, 7 (expe = 1) ams 0 1 sae0 0 1 dmacs 01 p74ddr 0 1 0 1 pin function p74 input pin p74 output pin p74 input pin p74 output pin dack0 output pin edack0 output pin mode 7 (expe = 0) ams sae0 0 1 dmacs 01 p74ddr 0101 pin function p74 input pin p74 output pin p74 input pin p74 output pin dack0 output pin
238 pin selection method and pin functions p73/ tend1 / etend1 the pin function is switched as shown below according to the combination of bit dmacs in pfcr2, bit tee1 in dmatcr of the dmac, bit etende in edmdr1 of the exdmac, and bit p73ddr. modes 1, 2, 4, 5, 6, 7 (expe = 1) etende 0 1 tee1 0 1 dmacs 01 p73ddr 0 1 0 1 pin function p73 input pin p73 output pin p73 input pin p73 output pin tend1 output pin etend1 output pin mode 7 (expe = 0) etende tee1 0 1 dmacs 01 p73ddr 0101 pin function p73 input pin p73 output pin p73 input pin p73 output pin tend1 output pin
239 pin selection method and pin functions p72/ tend0 / etend0 the pin function is switched as shown below according to the combination of bit dmacs in pfcr2, bit tee0 in dmatcr of the dmac, bit etende in edmdr0 of the exdmac, and bit p72ddr. modes 1, 2, 4, 5, 6, 7 (expe = 1) etende 0 1 tee0 0 1 dmacs 01 p72ddr 0 1 0 1 pin function p72 input pin p72 output pin p72 input pin p72 output pin tend0 output pin etend0 output pin mode 7 (expe = 0) etende tee0 0 1 dmacs 01 p72ddr 0101 pin function p72 input pin p72 output pin p72 input pin p72 output pin tend0 output pin p71/ dreq1 / edreq1 the pin function is switched as shown below according to bit p71ddr. p71ddr 0 1 pin function p71 input pin p71 output pin dreq1 input * edreq1 input note: * dreq1 input when dmacs = 1. p70/ dreq0 / edreq0 the pin function is switched as shown below according to bit p70ddr. p70ddr 0 1 pin function p70 input pin p70 output pin dreq0 input * edreq0 input note: * dreq0 input when dmacs = 1.
240 5.9 port 8 5.9.1 overview port 8 is a 6-bit i/o port. port 8 pins also function as interrupt input pins ( irq0 to irq5 ) and exdmac input/output pins ( edreq2 , etend2 , edack2 , edreq3 , etend3 , and edack3 ). the functions of pins p85 to p80 change according to the operating mode. the interrupt input pins ( irq0 to irq5 ) can be switched by making a setting in itsr. when pins p85 to p80 are used for irq input, they are schmitt-trigger inputs. figure 5.8 shows the port 8 pin configuration. p85 (i/o) / edack3 (output) / irq5 (input) p84 (i/o) / edack2 (output) / irq4 (input) p83 (i/o) / etend3 (output) / irq3 (input) p82 (i/o) / etend2 (output) / irq2 (input) p81 (i/o) / edreq3 (input) / irq1 (input) p80 (i/o) / edreq2 (input) / irq0 (input) modes 1, 2, 4, 5, 6, 7 (expe = 1) p85 (i/o) / edack3 (output) / irq5 (input) p84 (i/o) / edack2 (output) / irq4 (input) p83 (i/o) / etend3 (output) / irq3 (input) p82 (i/o) / etend2 (output) / irq2 (input) p81 (i/o) / edreq3 (input) / irq1 (input) p80 (i/o) / edreq2 (input) / irq0 (input) mode 7 (expe = 0) p85 (i/o) / irq5 (input) p84 (i/o) / irq4 (input) p83 (i/o) / irq3 (input) p82 (i/o) / irq2 (input) p81 (i/o) / irq1 (input) p80 (i/o) / irq0 (input) port 8 port 8 pins figure 5.8 port 8 pin functions
241 5.9.2 register configuration table 5.15 shows the port 8 register configuration. table 5.15 port 8 registers name abbreviation r/w initial value address * 1 port 8 data direction register p8ddr w h'00 * 2 h'fe27 port 8 data register p8dr r/w h'00 * 2 h'ff67 port 8 register port8 r undefined h'ff57 notes: 1. lower 16 bits of the address. 2. value of bits 5 to 0. port 8 data direction register (p8ddr) bit 76543210 p85ddr p84ddr p83ddr p82ddr p81ddr p80ddr initial value 00000000 read/write wwwwww p8ddr is a 6-bit write-only register, the individual bits of which specify input or output for the pins of port 8. p8ddr cannot be read; if it is, an undefined value will be read. bits 7 and 6 are reserved. setting a p8ddr bit to 1 makes the corresponding port 8 pin an output pin, while clearing the bit to 0 makes the pin an input pin. p8ddr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. port 8 data register (p8dr) bit 76543210 p85dr p84dr p83dr p82dr p81dr p80dr initial value 00000000 read/write r/w r/w r/w r/w r/w r/w p8dr is a 6-bit readable/writable register that stores output data for the port 8 pins (p85 to p80). bits 7 and 6 are reserved; they are always read as 0 and cannot be modified.
242 p8dr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. port 8 register (port8) bit 76543210 p85 p84 p83 p82 p81 p80 initial value undefined undefined * * * * * * read/write rrrrrr note: * determined by the state of pins p85 to p80. port8 is a 6-bit read-only register that shows the pin states. port8 cannot be written to; writing of output data for the port 8 pins (p85 to p80) must always be performed on p8dr. bits 7 and 6 are reserved; if read they will return an undefined value. if a port 8 read is performed while p8ddr bits are set to 1, the p8dr values are read. if a port 8 read is performed while p8ddr bits are cleared to 0, the pin states are read. after a reset and in hardware standby mode, port8 contents are determined by the pin states, as p8ddr and p8dr are initialized. port8 retains its prior state in software standby mode. 5.9.3 pin functions port 8 pins also function as interrupt input pins ( irq0 to irq5 ) and exdmac input/output pins ( edreq2 , etend2 , edack2 , edreq3 , etend3 , and edack3 ). port 8 pin functions are shown in table 5.16.
243 table 5.16 port 8 pin functions pin selection method and pin functions p85/ irq5 / edack3 the pin function is switched as shown below according to the combination of bit ams in edmdr3 of the exdmac, bit p85ddr, and bit its5 in itsr. modes 1, 2, 4, 5, 6, 7 (expe = 1) ams 0 1 p85ddr 0 1 pin function p85 input pin p85 output pin edack3 output irq5 interrupt input * mode 7 (expe = 0) ams p85ddr 0 1 pin function p85 input pin p85 output pin irq5 interrupt input * note: * irq5 input when its5 = 1. p84/ irq4 / edack2 the pin function is switched as shown below according to the combination of bit ams in edmdr2 of the exdmac, bit p84ddr, and bit its4 in itsr. modes 1, 2, 4, 5, 6, 7 (expe = 1) ams 0 1 p84ddr 0 1 pin function p84 input pin p84 input/output edack2 output irq4 interrupt input * mode 7 (expe = 0) ams p84ddr 0 1 pin function p84 input pin p84 output pin irq4 interrupt input * note: * irq4 input when its4 = 1.
244 pin selection method and pin functions p83/ irq3 / etend3 the pin function is switched as shown below according to the combination of bit etende in edmdr3 of the exdmac, bit p83ddr, and bit its3 in itsr. modes 1, 2, 4, 5, 6, 7 (expe = 1) etende 0 1 p83ddr 0 1 pin function p83 input pin p83 output pin etend3 output irq3 interrupt input * mode 7 (expe = 0) etende p83ddr 0 1 pin function p83 input pin p83 output pin irq3 interrupt input * note: * irq3 input when its3 = 1. p82/ irq2 / etend2 the pin function is switched as shown below according to the combination of bit etende in edmdr2 of the exdmac, bit p82ddr, and bit its2 in itsr. modes 1, 2, 4, 5, 6, 7 (expe = 1) etende 0 1 p82ddr 0 1 pin function p82 input pin p82 output pin etend2 output irq2 interrupt input * mode 7 (expe = 0) etende p82ddr 0 1 pin function p82 input pin p82 output pin irq2 interrupt input * note: * irq2 input when its2 = 1.
245 pin selection method and pin functions p81/ irq1 / edreq3 the pin function is switched as shown below according to the combination of bit p81ddr and bit its1 in itsr. p81ddr 0 1 pin function p81 input pin p81 output pin edreq3 input pin irq1 interrupt input * note: * irq1 input when its1 = 1. p80/ irq0 / edreq2 the pin function is switched as shown below according to the combination of bit p80ddr and bit its0 in itsr. p80ddr 0 1 pin function p80 input pin p80 output pin edreq2 input pin irq0 interrupt input * note: * irq0 input when its0 = 1.
246 5.10 port a 5.10.1 overview port a is an 8-bit i/o port. port a pins also function as address bus outputs. the pin functions change according to the operating mode. address output or port output can be selected with bits a23e to a16e in pfcr1. port a has a built-in mos input pull-up function that can be controlled by software. figure 5.9 shows the port a pin configuration. pa7 / a23 pa6 / a22 pa5 / a21 pa4 / a20 pa3 / a19 pa2 / a18 pa1 / a17 pa0 / a16 port a port a pins pa7 (i/o) / a23 (output) pa6 (i/o) / a22 (output) pa5 (i/o) / a21 (output) a20 (output) a19 (output) a18 (output) a17 (output) a16 (output) pin functions in modes 1, 2, 5, and 6 pa7 (i/o) / a23 (output) pa6 (i/o) / a22 (output) pa5 (i/o) / a21 (output) pa4 (i/o) / a20 (output) pa3 (i/o) / a19 (output) pa2 (i/o) / a18 (output) pa1 (i/o) / a17 (output) pa0 (i/o) / a16 (output) pin functions in modes 4 and 7 figure 5.9 port a pin functions
247 5.10.2 register configuration table 5.17 shows the port a register configuration. table 5.17 port a registers name abbreviation r/w initial value address * port a data direction register paddr w h'00 h'fe29 port a data register padr r/w h'00 h'ff69 port a register porta r undefined h'ff59 port a mos pull-up control register papcr r/w h'00 h'fe36 port a open-drain control register paodr r/w h'00 h'fe3d port function control register 1 pfcr1 r/w h'ff h'fe33 note: * lower 16 bits of the address. port a data direction register (paddr) bit 76543210 pa7ddr pa6ddr pa5ddr pa4ddr pa3ddr pa2ddr pa1ddr pa0ddr initial value 00000000 read/write wwwwwwww paddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port a. paddr cannot be read; if it is, an undefined value will be read. paddr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. the ope bit in sbycr is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. ? modes 1, 2, 5, and 6 pins pa4 to pa0 are address outputs regardless of the paddr settings. for pins pa7 to pa5, when the corresponding bit of a23e to a21e is set to 1, setting a paddr bit to 1 makes the corresponding port a pin an address output, while clearing the bit to 0 makes the pin an input port. clearing one of bits a23e to a21e to 0 makes the corresponding port a pin an i/o port, and its function can be switched with paddr.
248 ? mode 4 when the corresponding bit of a23e to a16e is set to 1, setting a paddr bit to 1 makes the corresponding port a pin an address output, while clearing the bit to 0 makes the pin an input port. clearing one of bits a23e to a16 to 0 makes the corresponding port a pin an i/o port, and its function can be switched with paddr. ? mode 7 (when bit expe is set to 1 in syscr) when the corresponding bit of a23e to a16e is set to 1, setting a paddr bit to 1 makes the corresponding port a pin an address output, while clearing the bit to 0 makes the pin an input port. clearing one of bits a23e to a16e to 0 makes the corresponding port a pin an i/o port; setting the corresponding paddr bit to 1 makes the pin an output port, while clearing the bit to 0 makes the pin an input port. ? mode 7 (when bit expe is cleared to 0 in syscr) port a is an i/o port, and its pin functions can be switched with paddr. port a data register (padr) bit 76543210 pa7dr pa6dr pa5dr pa4dr pa3dr pa2dr pa1dr pa0dr initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w padr is an 8-bit readable/writable register that stores output data for the port a pins (pa7 to pa0). padr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. port a register (porta) bit 76543210 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 initial value * * * * * * * * read/write rrrrrrrr note: * determined by the state of pins pa7 to pa0. porta is an 8-bit read-only register that shows the pin states. porta cannot be written to; writing of output data for the port a pins (pa7 to pa0) must always be performed on padr. if a port a read is performed while paddr bits are set to 1, the padr values are read. if a port a read is performed while paddr bits are cleared to 0, the pin states are read.
249 after a reset and in hardware standby mode, porta contents are determined by the pin states, as paddr and padr are initialized. porta retains its prior state in software standby mode. port a mos pull-up control register (papcr) bit 76543210 pa7pcr pa6pcr pa5pcr pa4pcr pa3pcr pa2pcr pa1pcr pa0pcr initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w papcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port a on a bit-by-bit basis. all the bits are valid in modes 4 and 7, and bits 7 to 5 are valid in modes 1, 2, 5, and 6. when a paddr bit is cleared to 0 (input port setting), setting the corresponding papcr bit to 1 turns on the mos input pull-up for the corresponding pin. papcr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. port a open drain control register (paodr) bit 76543210 pa7odr pa6odr pa5odr pa4odr pa3odr pa2odr pa1odr pa0odr initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w paodr is an 8-bit readable/writable register that controls whether pmos is on or off for each port a pin (pa7 to pa0). setting a paodr bit to 1 makes the corresponding port a pin an nmos open-drain output, while clearing the bit to 0 makes the pin a cmos output. paodr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. port function control register 1 (pfcr1) bit 76543210 a23e a22e a21e a20e a19e a18e a17e a16e initial value 11111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w
250 pfcr1 is an 8-bit readable/writable register that performs i/o port control. all the bits are valid in modes 4 and 7, and bits 7 to 5 are valid in modes 1, 2, 5, and 6. pfcr1 is initialized to h'ff by a reset and in hardware standby mode. it retains its prior state in software standby mode. bit 7?ddress 23 enable (a23e): enables or disables output for address output 23 (a23). bit 7 a23e description 0 dr output when pa7ddr = 1 1 a23 output when pa7ddr = 1 (initial value) bit 6?ddress 22 enable (a22e): enables or disables output for address output 22 (a22). bit 6 a22e description 0 dr output when pa6ddr = 1 1 a22 output when pa6ddr = 1 (initial value) bit 5?ddress 21 enable (a21e): enables or disables output for address output 21 (a21). bit 5 a21e description 0 dr output when pa5ddr = 1 1 a21 output when pa5ddr = 1 (initial value) bit 4?ddress 20 enable (a20e): enables or disables output for address output 20 (a20). valid only in modes 4 and 7. bit 4 a20e description 0 dr output when pa4ddr = 1 1 a20 output when pa4ddr = 1 (initial value) bit 3?ddress 19 enable (a19e): enables or disables output for address output 19 (a19). valid only in modes 4 and 7. bit 3 a19e description 0 dr output when pa3ddr = 1 1 a19 output when pa3ddr = 1 (initial value)
251 bit 2?ddress 18 enable (a18e): enables or disables output for address output 18 (a18). valid only in modes 4 and 7. bit 2 a18e description 0 dr output when pa2ddr = 1 1 a18 output when pa2ddr = 1 (initial value) bit 1?ddress 17 enable (a17e): enables or disables output for address output 17 (a17). valid only in modes 4 and 7. bit 1 a17e description 0 dr output when pa1ddr = 1 1 a17 output when pa1ddr = 1 (initial value) bit 0?ddress 16 enable (a16e): enables or disables output for address output 16 (a16). valid only in modes 4 and 7. bit 0 a16e description 0 dr output when pa0ddr = 1 1 a16 output when pa0ddr = 1 (initial value)
252 5.10.3 pin functions port a pins also function as address outputs. port a pin functions are shown in table 5.18. table 5.18 port a pin functions pin selection method and pin functions pa7/a23 pa6/a22 the pin function is switched as shown below according to the operating mode, bit expe, bits a23e to a21e, and bit paddr. pa5/a21 operating mode 1, 2, 4, 5, 6 7 expe 01 axxe 0 1 01 paddr 0 1 0 1010101 pin function pa input pin pa output pin pa input pin address output pin pa input pin pa output pin pa input pin pa output pin pa input pin address output pin pa4/a20 pa3/a19 the pin function is switched as shown below according to the operating mode, bit expe, bits a20e to a16e, and bit paddr. pa2/a18 pa1/a17 operating mode 1, 2, 5, 6 47 pa0/a16 expe 01 axxe 01 01 paddr 010 1 01010 1 pin function address output pin pa input pin pa output pin pa input pin address output pin pa input pin pa output pin pa input pin pa output pin pa input pin address output pin
253 5.10.4 mos input pull-up function port a has a built-in mos input pull-up function that can be controlled by software. this mos input pull-up function can be used by pins pa7 to pa5 in modes 1, 2, 5, and 6, and by all pins in modes 4 and 7. mos input pull-up can be specified as on or off on a bit-by-bit basis. when a paddr bit is cleared to 0, setting the corresponding papcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a reset and in hardware standby mode. the prior state is retained in software standby mode. table 5.19 summarizes the mos input pull-up states. table 5.19 mos input pull-up states (port a) mode reset hardware standby mode software standby mode in other operations 4, 7 pa7 to pa0 off off on/off on/off 1, 2, 5, 6 pa7 to pa5 on/off on/off pa4 to pa0 off off legend: off: mos input pull-up is always off. on/off: on when paddr = 0 and papcr = 1; otherwise off.
254 5.11 port b 5.11.1 overview port b is an 8-bit i/o port. port b pins also function as address bus outputs. the pin functions change according to the operating mode. port b has a built-in mos input pull-up function that can be controlled by software. figure 5.10 shows the port b pin configuration. pb7 / a15 pb6 / a14 pb5 / a13 pb4 / a12 pb3 / a11 pb2 / a10 pb1 / a9 pb0 / a8 port b port b pins a15 (output) a14 (output) a13 (output) a12 (output) a11 (output) a10 (output) a9 (output) a8 (output) pin functions in modes 1, 2, 5, and 6 pin functions in mode 4 pb7 (input) / a15 (output) pb6 (input) / a14 (output) pb5 (input) / a13 (output) pb4 (input) / a12 (output) pb3 (input) / a11 (output) pb2 (input) / a10 (output) pb1 (input) / a9 (output) pb0 (input) / a8 (output) pin functions in mode 7 pb7 (i/o) / a15 (output) pb6 (i/o) / a14 (output) pb5 (i/o) / a13 (output) pb4 (i/o) / a12 (output) pb3 (i/o) / a11 (output) pb2 (i/o) / a10 (output) pb1 (i/o) / a9 (output) pb0 (i/o) / a8 (output) figure 5.10 port b pin functions
255 5.11.2 register configuration table 5.20 shows the port b register configuration. table 5.20 port b registers name abbreviation r/w initial value address * port b data direction register pbddr w h'00 h'fe2a port b data register pbdr r/w h'00 h'ff6a port b register portb r undefined h'ff5a port b mos pull-up control register pbpcr r/w h'00 h'fe37 note: * lower 16 bits of the address. port b data direction register (pbddr) bit 76543210 pb7ddr pb6ddr pb5ddr pb4ddr pb3ddr pb2ddr pb1ddr pb0ddr initial value 00000000 read/write wwwwwwww pbddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port b. pbddr cannot be read; if it is, an undefined value will be read. pbddr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. the ope bit in sbycr is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. ? modes 1, 2, 5, and 6 port b pins are address outputs regardless of the pbddr settings. ? mode 4 setting a pbddr bit to 1 makes the corresponding port b pin an address output, while clearing the bit to 0 makes the pin an input port. ? mode 7 (when bit expe is set to 1 in syscr) setting a pbddr bit to 1 makes the corresponding port b pin an address output, while clearing the bit to 0 makes the pin an input port. ? mode 7 (when bit expe is cleared to 0 in syscr) port b is an i/o port, and its pin functions can be switched with pbddr.
256 port b data register (pbdr) bit 76543210 pb7dr pb6dr pb5dr pb4dr pb3dr pb2dr pb1dr pb0dr initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pbdr is an 8-bit readable/writable register that stores output data for the port b pins (pb7 to pb0). pbdr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. port b register (portb) bit 76543210 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 initial value * * * * * * * * read/write rrrrrrrr note: * determined by the state of pins pb7 to pb0. portb is an 8-bit read-only register that shows the pin states. portb cannot be written to; writing of output data for the port b pins (pb7 to pb0) must always be performed on pbdr. if a port b read is performed while pbddr bits are set to 1, the pbdr values are read. if a port b read is performed while pbddr bits are cleared to 0, the pin states are read. after a reset and in hardware standby mode, portb contents are determined by the pin states, as pbddr and pbdr are initialized. portb retains its prior state in software standby mode. port b mos pull-up control register (pbpcr) bit 76543210 pb7pcr pb6pcr pb5pcr pb4pcr pb3pcr pb2pcr pb1pcr pb0pcr initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pbpcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port b on a bit-by-bit basis.
257 in modes 4 and 7, when a pbddr bit is cleared to 0 (input port setting), setting the corresponding pbpcr bit to 1 turns on the mos input pull-up for the corresponding pin. pbpcr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. 5.11.3 pin functions port b pins also function as address outputs. port b pin functions are shown in table 5.21. table 5.21 port b pin functions pin selection method and pin functions pb7/a15 pb6/a14 the pin function is switched as shown below according to the operating mode, bit expe, and bit pbddr. pb5/a13 pb4/a12 operating mode 1, 2, 5, 6 47 pb3/a11 expe 01 pb2/a10 pbddr 0 1 010 1 pb1/a9 pb0/a8 pin function address output pin pb input pin address output pin pb input pin pb output pin pb input pin address output pin
258 5.11.4 mos input pull-up function port b has a built-in mos input pull-up function that can be controlled by software. this mos input pull-up function can be used in modes 4 and 7. mos input pull-up can be specified as on or off on a bit-by-bit basis. in modes 4 and 7, when a pbddr bit is cleared to 0, setting the corresponding pbpcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a reset and in hardware standby mode. the prior state is retained in software standby mode. table 5.22 summarizes the mos input pull-up states. table 5.22 mos input pull-up states (port b) mode reset hardware standby mode software standby mode in other operations 1, 2, 5, 6 off off off off 4, 7 on/off on/off legend: off: mos input pull-up is always off. on/off: on when pbddr = 0 and pbpcr = 1; otherwise off.
259 5.12 port c 5.12.1 overview port c is an 8-bit i/o port. port c pins also function as address bus outputs. the pin functions change according to the operating mode. port c has a built-in mos input pull-up function that can be controlled by software. figure 5.11 shows the port c pin configuration. pc7 / a7 pc6 / a6 pc5 / a5 pc4 / a4 pc3 / a3 pc2 / a2 pc1 / a1 pc0 / a0 port c port c pins a7 (output) a6 (output) a5 (output) a4 (output) a3 (output) a2 (output) a1 (output) a0 (output) pin functions in modes 1, 2, 5, and 6 pin functions in mode 4 pc7 (input) / a7 (output) pc6 (input) / a6 (output) pc5 (input) / a5 (output) pc4 (input) / a4 (output) pc3 (input) / a3 (output) pc2 (input) / a2 (output) pc1 (input) / a1 (output) pc0 (input) / a0 (output) pin functions in mode 7 pc7 (i/o) / a7 (output) pc6 (i/o) / a6 (output) pc5 (i/o) / a5 (output) pc4 (i/o) / a4 (output) pc3 (i/o) / a3 (output) pc2 (i/o) / a2 (output) pc1 (i/o) / a1 (output) pc0 (i/o) / a0 (output) figure 5.11 port c pin functions
260 5.12.2 register configuration table 5.23 shows the port c register configuration. table 5.23 port c registers name abbreviation r/w initial value address * port c data direction register pcddr w h'00 h'fe2b port c data register pcdr r/w h'00 h'ff6b port c register portc r undefined h'ff5b port c mos pull-up control register pcpcr r/w h'00 h'fe38 note: * lower 16 bits of the address. port c data direction register (pcddr) bit 76543210 pc7ddr pc6ddr pc5ddr pc4ddr pc3ddr pc2ddr pc1ddr pc0ddr initial value 00000000 read/write wwwwwwww pcddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port c. pcddr cannot be read; if it is, an undefined value will be read. pcddr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. the ope bit in sbycr is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. ? modes 1, 2, 5, and 6 port c pins are address outputs regardless of the pcddr settings. ? mode 4 setting a pcddr bit to 1 makes the corresponding port c pin an address output, while clearing the bit to 0 makes the pin an input port. ? mode 7 (when bit expe is set to 1 in syscr) setting a pcddr bit to 1 makes the corresponding port c pin an address output, while clearing the bit to 0 makes the pin an input port. ? mode 7 (when bit expe is cleared to 0 in syscr) port c is an i/o port, and its pin functions can be switched with pcddr.
261 port c data register (pcdr) bit 76543210 pc7dr pc6dr pc5dr pc4dr pc3dr pc2dr pc1dr pc0dr initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pcdr is an 8-bit readable/writable register that stores output data for the port c pins (pc7 to pc0). pcdr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. port c register (portc) bit 76543210 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 initial value * * * * * * * * read/write rrrrrrrr note: * determined by the state of pins pc7 to pc0. portc is an 8-bit read-only register that shows the pin states. portc cannot be written to; writing of output data for the port c pins (pc7 to pc0) must always be performed on pcdr. if a port c read is performed while pcddr bits are set to 1, the pcdr values are read. if a port c read is performed while pcddr bits are cleared to 0, the pin states are read. after a reset and in hardware standby mode, portc contents are determined by the pin states, as pcddr and pcdr are initialized. portc retains its prior state in software standby mode. port c mos pull-up control register (pcpcr) bit 76543210 pc7pcr pc6pcr pc5pcr pc4pcr pc3pcr pc2pcr pc1pcr pc0pcr initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pcpcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port c on a bit-by-bit basis.
262 in modes 4 and 7, when a pcddr bit is cleared to 0 (input port setting), setting the corresponding pcpcr bit to 1 turns on the mos input pull-up for the corresponding pin. pcpcr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. 5.12.3 pin functions port c pins also function as address outputs. port c pin functions are shown in table 5.24. table 5.24 port c pin functions pin selection method and pin functions pc7/a7 pc6/a6 the pin function is switched as shown below according to the operating mode, bit expe, and bit pcddr. pc5/a5 pc4/a4 operating mode 1, 2, 5, 6 47 pc3/a3 expe 01 pc2/a2 pcddr 0 1 010 1 pc1/a1 pc0/a0 pin function address output pin pc input pin address output pin pc input pin pc output pin pc input pin address output pin
263 5.12.4 mos input pull-up function port c has a built-in mos input pull-up function that can be controlled by software. this mos input pull-up function can be used in modes 4 and 7. mos input pull-up can be specified as on or off on a bit-by-bit basis. in modes 4 and 7, when a pcddr bit is cleared to 0, setting the corresponding pcpcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a reset and in hardware standby mode. the prior state is retained in software standby mode. table 5.25 summarizes the mos input pull-up states. table 5.25 mos input pull-up states (port c) mode reset hardware standby mode software standby mode in other operations 1, 2, 5, 6 off off off off 4, 7 on/off on/off legend: off: mos input pull-up is always off. on/off: on when pcddr = 0 and pcpcr = 1; otherwise off.
264 5.13 port d 5.13.1 overview port d is an 8-bit i/o port. port d pins also function as data bus input/output pins. the pin functions change according to the operating mode. port d has a built-in mos input pull-up function that can be controlled by software. figure 5.12 shows the port d pin configuration. pd7 / d15 pd6 / d14 pd5 / d13 pd4 / d12 pd3 / d11 pd2 / d10 pd1 / d9 pd0 / d8 port d port d pins d15 (i/o) d14 (i/o) d13 (i/o) d12 (i/o) d11 (i/o) d10 (i/o) d9 (i/o) d8 (i/o) pin functions in modes 1, 2, 4, 5, and 6 pin functions in mode 7 pd7 (i/o) / d15 (i/o) pd6 (i/o) / d14 (i/o) pd5 (i/o) / d13 (i/o) pd4 (i/o) / d12 (i/o) pd3 (i/o) / d11 (i/o) pd2 (i/o) / d10 (i/o) pd1 (i/o) / d9 (i/o) pd0 (i/o) / d8 (i/o) figure 5.12 port d pin functions
265 5.13.2 register configuration table 5.26 shows the port d register configuration. table 5.26 port d registers name abbreviation r/w initial value address * port d data direction register pdddr w h'00 h'fe2c port d data register pddr r/w h'00 h'ff6c port d register portd r undefined h'ff5c port d mos pull-up control register pdpcr r/w h'00 h'fe39 note: * lower 16 bits of the address. port d data direction register (pdddr) bit 76543210 pd7ddr pd6ddr pd5ddr pd4ddr pd3ddr pd2ddr pd1ddr pd0ddr initial value 00000000 read/write wwwwwwww pdddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port d. pdddr cannot be read; if it is, an undefined value will be read. pdddr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. ? modes 1, 2, 4, 5, and 6 the input/output direction specification by pdddr is ignored, and port d is automatically designated for data input/output. ? mode 7 (when bit expe is set to 1 in syscr) the input/output direction specification by pdddr is ignored, and port d is automatically designated for data input/output. ? mode 7 (when bit expe is cleared to 0 in syscr) port d is an i/o port, and its pin functions can be switched with pdddr.
266 port d data register (pddr) bit 76543210 pd7dr pd6dr pd5dr pd4dr pd3dr pd2dr pd1dr pd0dr initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pddr is an 8-bit readable/writable register that stores output data for the port d pins (pd7 to pd0). pddr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. port d register (portd) bit 76543210 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 initial value * * * * * * * * read/write rrrrrrrr note: * determined by the state of pins pd7 to pd0. portd is an 8-bit read-only register that shows the pin states. portd cannot be written to; writing of output data for the port d pins (pd7 to pd0) must always be performed on pddr. if a port d read is performed while pdddr bits are set to 1, the pddr values are read. if a port d read is performed while pdddr bits are cleared to 0, the pin states are read. after a reset and in hardware standby mode, portd contents are determined by the pin states, as pdddr and pddr are initialized. portd retains its prior state in software standby mode. port d mos pull-up control register (pdpcr) bit 76543210 pd7pcr pd6pcr pd5pcr pd4pcr pd3pcr pd2pcr pd1pcr pd0pcr initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pdpcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port d on a bit-by-bit basis.
267 in mode 7, when a pdddr bit is cleared to 0 (input port setting), setting the corresponding pdpcr bit to 1 turns on the mos input pull-up for the corresponding pin. pdpcr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. 5.13.3 pin functions port d pins also function as data input/output pins. port d pin functions are shown in table 5.27. table 5.27 port d pin functions pin selection method and pin functions pd7/d15 pd6/d14 the pin function is switched as shown below according to the operating mode, bit expe, and bit pdddr. pd5/d13 pd4/d12 operating mode 1, 2, 4, 5, 6 7 pd3/d11 expe 01 pd2/d10 pdddr 01 pd1/d9 pin function data i/o pin pd input pin pd output pin data i/o pin pd0/d8
268 5.13.4 mos input pull-up function port d has a built-in mos input pull-up function that can be controlled by software. this mos input pull-up function can be used in mode 7. mos input pull-up can be specified as on or off on a bit-by-bit basis. in mode 7, when a pdddr bit is cleared to 0, setting the corresponding pdpcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a reset and in hardware standby mode. the prior state is retained in software standby mode. table 5.28 summarizes the mos input pull-up states. table 5.28 mos input pull-up states (port d) mode reset hardware standby mode software standby mode in other operations 1, 2, 4, 5, 6 off off off off 7 on/off on/off legend: off: mos input pull-up is always off. on/off: on when pdddr = 0 and pdpcr = 1; otherwise off.
269 5.14 port e 5.14.1 overview port e is an 8-bit i/o port. port e pins also function as data bus input/output pins. the pin functions change according to the operating mode and the bus mode (8-bit or 16-bit). port e has a built-in mos input pull-up function that can be controlled by software. figure 5.13 shows the port e pin configuration. pe7 / d7 pe6 / d6 pe5 / d5 pe4 / d4 pe3 / d3 pe2 / d2 pe1 / d1 pe0 / d0 port e port e pins d7 (i/o) d6 (i/o) d5 (i/o) d4 (i/o) d3 (i/o) d2 (i/o) d1 (i/o) d0 (i/o) pin functions in modes 1 and 5 pin functions in modes 2, 4, 6, and 7 pe7 (i/o) / d7 (i/o) pe6 (i/o) / d6 (i/o) pe5 (i/o) / d5 (i/o) pe4 (i/o) / d4 (i/o) pe3 (i/o) / d3 (i/o) pe2 (i/o) / d2 (i/o) pe1 (i/o) / d1 (i/o) pe0 (i/o) / d0 (i/o) figure 5.13 port e pin functions
270 5.14.2 register configuration table 5.29 shows the port e register configuration. table 5.29 port e registers name abbreviation r/w initial value address * port e data direction register peddr w h'00 h'fe2d port e data register pedr r/w h'00 h'ff6d port e register porte r undefined h'ff5d port e mos pull-up control register pepcr r/w h'00 h'fe3a note: * lower 16 bits of the address. port e data direction register (peddr) bit 76543210 pe7ddr pe6ddr pe5ddr pe4ddr pe3ddr pe2ddr pe1ddr pe0ddr initial value 00000000 read/write wwwwwwww peddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port e. peddr cannot be read; if it is, an undefined value will be read. peddr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. ? modes 1, 2, 4, 5, and 6 when 8-bit bus mode is selected, port e functions as an i/o port. the pin states can be changed with peddr. when 16-bit bus mode is selected, the input/output direction specification by peddr is ignored and port e is designated for data input/output. for details of 8-bit and 16-bit bus modes, see section 4, bus controller. ? mode 7 (when bit expe is set to 1 in syscr) when 8-bit bus mode is selected, port e functions as an i/o port. setting a peddr bit to 1 makes the corresponding port e pin an output port, while clearing the bit to 0 makes the pin an input port. when 16-bit bus mode is selected, the input/output direction specification by peddr is ignored and port e is designated for data input/output. ? mode 7 (when bit expe is cleared to 0 in syscr) port e is an i/o port, and its pin functions can be switched with peddr.
271 port e data register (pedr) bit 76543210 pe7dr pe6dr pe5dr pe4dr pe3dr pe2dr pe1dr pe0dr initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pedr is an 8-bit readable/writable register that stores output data for the port e pins (pe7 to pe0). pedr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. port e register (porte) bit 76543210 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 initial value * * * * * * * * read/write rrrrrrrr note: * determined by the state of pins pe7 to pe0. porte is an 8-bit read-only register that shows the pin states. porte cannot be written to; writing of output data for the port e pins (pe7 to pe0) must always be performed on pedr. if a port e read is performed while peddr bits are set to 1, the pedr values are read. if a port e read is performed while peddr bits are cleared to 0, the pin states are read. after a reset and in hardware standby mode, porte contents are determined by the pin states, as peddr and pedr are initialized. porte retains its prior state in software standby mode. port e mos pull-up control register (pepcr) bit 76543210 pe7pcr pe6pcr pe5pcr pe4pcr pe3pcr pe2pcr pe1pcr pe0pcr initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pepcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port e on a bit-by-bit basis. in 8-bit bus mode, when a peddr bit is cleared to 0 (input port setting), setting the corresponding pepcr bit to 1 turns on the mos input pull-up for the corresponding pin.
272 pepcr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. 5.14.3 pin functions port e pins also function as data input/output pins. port e pin functions are shown in table 5.30. table 5.30 port e pin functions pin selection method and pin functions pe7/d7 pe6/d6 the pin function is switched as shown below according to the operating mode, the bus mode, bit expe, and bit peddr. pe5/d5 pe4/d4 operating mode 1, 2, 4, 5, 6 7 pe3/d3 pe2/d2 pe1/d1 bus mode all areas 8-bit space at least one area 16-bit space all areas 8-bit space at least one area 16-bit space pe0/d0 expe 011 peddr 0 1 0101 pin function pe input pin pe output pin data i/o pin pe input pin pe output pin pe input pin pe output pin data i/o pin
273 5.14.4 mos input pull-up function port e has a built-in mos input pull-up function that can be controlled by software. this mos input pull-up function can be used in 8-bit bus mode. mos input pull-up can be specified as on or off on a bit-by-bit basis. in 8-bit bus mode, when a peddr bit is cleared to 0, setting the corresponding pepcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a reset and in hardware standby mode. the prior state is retained in software standby mode. table 5.31 summarizes the mos input pull-up states. table 5.31 mos input pull-up states (port e) mode reset hardware standby mode software standby mode in other operations 1, 2, 4 to 7 8-bit bus off off on/off on/off 16-bit bus off off legend: off: mos input pull-up is always off. on/off: on when peddr = 0 and pepcr = 1; otherwise off.
274 5.15 port f 5.15.1 overview port f is an 8-bit i/o port. port f pins also function as interrupt input pins ( irq14 and irq15 ), bus control signal input/output pins ( as , rd , hwr , lwr , lcas , ucas , and wait ), and the system clock (? output pin. the as and lwr output pins can be switched by making a setting in pfcr2. figure 5.14 shows the port f pin configuration. pf7 / pf6 / as pf5 / rd pf4 / hwr pf3 / lwr pf2 / lcas / irq15 pf1 / ucas / irq14 pf0 / wait port f port f pins pf7 (input) / (output) pf6 (i/o) / as (output) rd (output) hwr (output) pf3 (i/o) / lwr (output) pf2 (i/o) / lcas (output) / irq15 (input) pf1 (i/o) / ucas (output) / irq14 (input) pf0 (i/o) / wait (input) pin functions in modes 1, 2, 4, 5, and 6 pin functions in mode 7 pf7 (input) / (output) pf6 (i/o) / as (output) pf5 (i/o) / rd (output) pf4 (i/o) / hwr (output) pf3 (i/o) / lwr (output) pf2 (i/o) / lcas (output) / irq15 (input) pf1 (i/o) / ucas (output) / irq14 (input) pf0 (i/o) / wait (input) figure 5.14 port f pin functions
275 5.15.2 register configuration table 5.32 shows the port f register configuration. table 5.32 port f registers name abbreviation r/w initial value address * 1 port f data direction register pfddr w h'80/h'00 * 2 h'fe2e port f data register pfdr r/w h'00 h'ff6e port f register portf r undefined h'ff5e port function control register 2 pfcr2 r/w h'0e h'fe34 notes: 1. lower 16 bits of the address. 2. initial value depends on the mode. port f data direction register (pfddr) bit 76543210 pf7ddr pf6ddr pf5ddr pf4ddr pf3ddr pf2ddr pf1ddr pf0ddr modes 1, 2, 4, 5, 6 initial value 10000000 read/write wwwwwwww mode 7 initial value 00000000 read/write wwwwwwww pfddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port f. pfddr cannot be read; if it is, an undefined value will be read. pfddr is initialized by a reset and in hardware standby mode, to h'80 in modes 1, 2, 4, 5, and 6, and to h'00 in mode 7. it retains its prior state in software standby mode. the ope bit in sbycr is used to select whether the bus control output pins retain their output state or become high- impedance when a transition is made to software standby mode. ? modes 1, 2, 4, 5, and 6 pin pf7 functions as the ?output pin when the corresponding pfddr bit is set to 1, and as an input port when the bit is cleared to 0. pin pf6 functions as the as output pin when asoe is set to 1. when asoe is cleared to 0, pin pf6 is an i/o port and its function can be switched with pf6ddr. the input/output direction specification in pfddr is ignored for pins pf5 and pf4, which are automatically designated as bus control outputs ( rd and hwr ).
276 pin pf3 functions as the lwr output pin when lwroe is set to 1. when lwroe is cleared to 0, pin pf3 is an i/o port and its function can be switched with pf3ddr. pins pf2 to pf0 function as bus control input/output pins ( lcas , ucas , and wait ) when the appropriate bus controller settings are made. otherwise, these pins are output ports when the corresponding pfddr bit is set to 1, and input ports when the bit is cleared to 0. ? mode 7 (when bit expe is set to 1 in syscr) pin pf7 functions as the ?output pin when the corresponding pfddr bit is set to 1, and as an input port when the bit is cleared to 0. pin pf6 functions as the as output pin when asoe is set to 1. when asoe is cleared to 0, pin pf6 is an i/o port and its function can be switched with pf6ddr. the input/output direction specification in pfddr is ignored for pins pf5 and pf4, which are automatically designated as bus control outputs ( rd and hwr ). pin pf3 functions as the lwr output pin when lwroe is set to 1. when lwroe is cleared to 0, pin pf3 is an i/o port and its function can be switched with pf3ddr. pins pf2 to pf0 function as bus control input/output pins ( lcas , ucas , and wait ) when the appropriate pfcr2 settings are made. otherwise, these pins are i/o ports, and their functions can be switched with pfddr. ? mode 7 (when bit expe is cleared to 0 in syscr) pin pf7 functions as the ?output pin when the corresponding pfddr bit is set to 1, and as an input port when the bit is cleared to 0. pins pf6 to pf0 are i/o ports, and their functions can be switched with pfddr. port f data register (pfdr) bit 76543210 pf7dr pf6dr pf5dr pf4dr pf3dr pf2dr pf1dr pf0dr initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pfdr is an 8-bit readable/writable register that stores output data for the port f pins (pf7 to pf0). pfdr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode.
277 port f register (portf) bit 76543210 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 initial value * * * * * * * * read/write rrrrrrrr note: * determined by the state of pins pf7 to pf0. portf is an 8-bit read-only register that shows the pin states. portf cannot be written to; writing of output data for the port f pins (pf7 to pf0) must always be performed on pfdr. if a port f read is performed while pfddr bits are set to 1, the pfdr values are read. if a port f read is performed while pfddr bits are cleared to 0, the pin states are read. after a reset and in hardware standby mode, portf contents are determined by the pin states, as pfddr and pfdr are initialized. portf retains its prior state in software standby mode. port function control register 2 (pfcr2) bit 76543210 asoe lwroe oes dmacs initial value 00001110 read/write r/w r/w r/w r/w pfcr2 is an 8-bit readable/writable register that performs i/o port control. pfcr2 is initialized to h'0e by a reset and in hardware standby mode. it retains its prior state in software standby mode. bits 7 to 4?eserved: these bits are always read as 0, and should only be written with 0. bit 3?s output enable (asoe): enables or disables as output. bit 3 asoe description 0 pf6 is designated as i/o port and does not function as as output pin 1 pf6 is designated as as output pin (initial value)
278 bit 2?wr output enable (lwroe): enables or disables lwr output. bit 2 lwroe description 0 pf3 is designated as i/o port and does not function as lwr output pin 1 pf3 is designated as lwr output pin (initial value) bit 1?e output select (oes): selects the oe output pin port when the oee bit is set to 1 in dramcr (enabling oe output). bit 1 oes description 0 p35 is designated as oe output pin 1 ph3 is designated as oe output pin (initial value) bit 0?mac control pin select (dmacs): selects the dmac control i/o port. bit 0 dmacs description 0 p65 to p60 are designated as dmac control pins (initial value) 1 p75 to p70 are designated as dmac control pins 5.15.3 pin functions port f pins also function as interrupt input pins ( irq14 and irq15 ), bus control signal input/output pins ( as , rd , hwr , lwr , lcas , ucas , and wait ), and the system clock (? output pin. port f pin functions are shown in table 5.33.
279 table 5.33 port f pin functions pin selection method and pin functions pf7/ the pin function is switched as shown below according to bit pf7ddr. operating mode 1, 2, 4, 5, 6, 7 pfddr 0 1 pin function pf7 input pin output pin pf6/ as the pin function is switched as shown below according to the operating mode, bit expe, bit pf6ddr, and bit asoe. operating mode 1, 2, 4, 5, 6 7 expe 01 asoe 1 0 10 pf6ddr 0 101 01 pin function as output pin pf6 input pin pf6 output pin pf6 input pin pf6 output pin as output pin pf6 input pin pf6 output pin pf5/ rd the pin function is switched as shown below according to the operating mode, bit expe, and bit pf5ddr. operating mode 1, 2, 4, 5, 6 7 expe 01 pf5ddr 01 pin function rd output pin pf5 input pin pf5 output pin rd output pin pf4/ hwr the pin function is switched as shown below according to the operating mode, bit expe, and bit pf4ddr. operating mode 1, 2, 4, 5, 6 7 expe 01 pf4ddr 01 pin function hwr output pin pf4 input pin pf4 output pin hwr output pin
280 pin selection method and pin functions pf3/ lwr the pin function is switched as shown below according to the operating mode, bit expe, bit pf3ddr, and bit lwroe. operating mode 1, 2, 4, 5, 6 7 expe 01 lwrod 1 0 10 pf3ddr 0 101 01 pin function lwr output pin pf3 input pin pf3 output pin pf3 input pin pf3 output pin lwr output pin pf3 input pin pf3 output pin pf2/ lcas / irq15 the pin function is switched as shown below according to the combination of the operating mode, bit expe, bits rmts2 to rmts0 in dramcr, bits abw5 to abw2 in abwcr, and bit pf2ddr. operating mode 1, 2, 4, 5, 6 7 expe 01 areas 2 to 5 any dram space area is 16-bit bus space all dram space areas are 8-bit bus space, or areas 2 to 5 are all normal space any dram space area is 16-bit bus space all dram space areas are 8-bit bus space, or areas 2 to 5 are all normal space pf2ddr 0 101 01 pin function lcas output pin pf2 input pin pf2 output pin pf2 input pin pf2 output pin lcas output pin pf2 input pin pf2 output pin irq15 interrupt input pin * note: * irq15 interrupt input pin when bit its15 is cleared to 0 in itsr.
281 pin selection method and pin functions pf1/ ucas / irq14 the pin function is switched as shown below according to the combination of the operating mode, bit expe, bits rmts2 to rmts0 in dramcr, and bit pf1ddr. operating mode 1, 2, 4, 5, 6 7 expe 01 areas 2 to 5 any of areas 2 to 5 is dram space areas 2 to 5 are all normal space any of areas 2 to 5 is dram space areas 2 to 5 are all normal space pf1ddr 0 101 01 pin function ucas output pin pf1 input pin pf1 output pin pf1 input pin pf1 output pin ucas output pin pf1 input pin pf1 output pin irq14 interrupt pin * note: * irq14 interrupt input pin when bit its14 is cleared to 0 in itsr. pf0/ wait the pin function is switched as shown below according to the operating mode, bit expe, bit waite, and bit pf0ddr. operating mode 1, 2, 4, 5, 6 7 expe 01 waite 0 1 01 pf0ddr 0 1 01 01 pin function pf0 input pin pf0 output pin wait input pin pf0 input pin pf0 output pin pf0 input pin pf0 output pin wait input pin
282 5.16 port g 5.16.1 overview port g is a 7-bit i/o port. port g pins also function as bus control signal output pins ( breq , back , breqo , and cs3 to cs0 ). cs3 to cs0 output can be enabled or disabled by making a setting in pfcr0. figure 5.15 shows the port g pin configuration. pg6 / breq pg5 / back pg4 / breqo pg3 / cs3 pg2 / cs2 pg1 / cs1 pg0 / cs0 port g port g pins pin functions in modes 1, 2, 4, 5, 6, and 7 pg6 (i/o) / breq (input) pg5 (i/o) / back (output) pg4 (i/o) / breqo (output) pg3 (i/o) / cs3 (output) pg2 (i/o) / cs2 (output) pg1 (i/o) / cs1 (output) pg0 (i/o) / cs0 (output) figure 5.15 port g pin functions 5.16.2 register configuration table 5.34 shows the port g register configuration. table 5.34 port g registers name abbreviation r/w initial value address * 1 port g data direction register pgddr w h'01/h'00 * 2 h'fe2f port g data register pgdr r/w h'00 h'ff6f port g register portg r undefined h'ff5f port function control register 0 pfcr0 r/w h'ff h'fe32 notes: 1. lower 16 bits of the address. 2. initial value depends on the mode.
283 port g data direction register (pgddr) bit 76543210 pg6ddr pg5ddr pg4ddr pg3ddr pg2ddr pg1ddr pg0ddr modes 1, 2, 5, 6 initial value 00000001 read/write wwwwwww modes 4 and 7 initial value 00000000 read/write wwwwwww pgddr is a 7-bit write-only register, the individual bits of which specify input or output for the pins of port g. pgddr cannot be read. bit 7 is reserved. pgddr is initialized by a reset and in hardware standby mode, to h'01 in modes 1, 2, 5, and 6, and to h'00 in modes 4 and 7. it retains its prior state in software standby mode. the ope bit in sbycr is used to select whether the bus control output pins retain their output state or become high-impedance when a transition is made to software standby mode. ? modes 1, 2, 4, 5, and 6 when the cs output enable bits (cs3e to cs0e) are set to 1, pins pg3 to pg0 function as cs output pins when the corresponding pgddr bit is set to 1, and as input ports when the bit is cleared to 0. when cs3e to cs0e are cleared to 0, pins pg3 to pg0 are i/o ports, and their functions can be switched with pgddr. pins pg6 to pg4 function as bus control input/output pins ( breqo , back , and breq ) when the appropriate bus controller settings are made. otherwise, these pins are i/o ports, and their functions can be switched with pgddr. ? mode 7 (when bit expe is set to 1 in syscr) when the cs output enable bits (cs3e to cs0e) are set to 1, pins pg3 to pg0 function as cs output pins when the corresponding pgddr bit is set to 1, and as input ports when the bit is cleared to 0. when cs3e to cs0e are cleared to 0, pins pg3 to pg0 are i/o ports, and their functions can be switched with pgddr. pins pg6 to pg4 function as bus control input/output pins ( breqo , back , and breq ) when the appropriate bus controller settings are made. otherwise, these pins are output ports when the corresponding pgddr bit is set to 1, and as input ports when the bit is cleared to 0. ? mode 7 (when bit expe is cleared to 0 in syscr) pins pg6 to pg0 are i/o ports, and their functions can be switched with pgddr.
284 port g data register (pgdr) bit 76543210 pg6dr pg5dr pg4dr pg3dr pg2dr pg1dr pg0dr initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w pgdr is a 7-bit readable/writable register that stores output data for the port g pins (pg6 to pg0). bit 7 is reserved; it is always read as 0, and cannot be modified. pgdr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. port g register (portg) bit 76543210 pg6 pg5 pg4 pg3 pg2 pg1 pg0 initial value undefined * * * * * * * read/write rrrrrrrr note: * determined by the state of pins pg6 to pg0. portg is a 7-bit read-only register that shows the pin states. portg cannot be written to; writing of output data for the port g pins (pg6 to pg0) must always be performed on pgdr. bit 7 is reserved; if read it will return an undefined value. if a port g read is performed while pgddr bits are set to 1, the pgdr values are read. if a port g read is performed while pgddr bits are cleared to 0, the pin states are read. after a reset and in hardware standby mode, portg contents are determined by the pin states, as pgddr and pgdr are initialized. portg retains its prior state in software standby mode. port function control register 0 (pfcr0) bit 76543210 cs7e cs6e cs5e cs4e cs3e cs2e cs1e cs0e initial value 11111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w pfcr0 is an 8-bit readable/writable register that performs i/o port control. pfcr0 is initialized to h'ff by a reset and in hardware standby mode. it retains its prior state in software standby mode.
285 bits 7 to 0?s7 to cs0 enable (cs7e to cs0e): these bits enable or disable the corresponding csn output. bit n csne description 0 pin is designated as i/o port and does not function as csn output pin 1 pin is designated as csn output pin (initial value) (n = 7 to 0) 5.16.3 pin functions port g pins also function as bus control signal output pins ( breq , back, breqo , and cs3 to cs0 ). port g pin functions are shown in table 5.35. table 5.35 port g pin functions pin selection method and pin functions pg6/ breq the pin function is switched as shown below according to the operating mode, bit expe, bit brle, and bit pg6ddr. operating mode 1, 2, 4, 5, 6 7 expe 01 brle 0 1 01 pg6ddr 0 1 0101 pin function pg6 input pin pg6 output pin breq input pin pg6 input pin pg6 output pin pg6 input pin pg6 output pin breq input pin pg5/ back the pin function is switched as shown below according to the operating mode, bit expe, bit brle, and bit pg5ddr. operating mode 1, 2, 4, 5, 6 7 expe 01 brle 0 1 01 pg5ddr 0 1 0101 pin function pg5 input pin pg5 output pin back output pin pg5 input pin pg5 output pin pg5 input pin pg5 output pin back output pin
286 pin selection method and pin functions pg4/ breqo the pin function is switched as shown below according to the operating mode, bit expe, bit brle, bit breqoe, and bit pg4ddr. operating mode 1, 2, 4, 5, 6 7 expe 01 brle 0 1 01 breqoe 01 01 pg4ddr 0 1 0 1 010101 pin function pg4 input pin pg4 output pin pg4 input pin pg4 output pin breqo output pin pg4 input pin pg4 output pin pg4 input pin pg4 output pin pg4 input pin pg4 output pin breqo output pin pg3/ cs3 pg2/ cs2 the pin function is switched as shown below according to the operating mode, bit pgnddr, bit csne, and bits rmts2 to rmts0. operating mode 1, 2, 4, 5, 6 7 expe 01 csne 0 1 01 rmts2 to rmts0 area n in dram space area n in normal space area n in dram space area n in normal space pgnddr 0 1 010101 01 pin function pgn input pin pgn output pin rasn output pin pgn input pin csn output pin pgn input pin pgn output pin pgn input pin pgn output pin rasn output pin pgn input pin csn output pin (n = 3 or 2) pg1/ cs1 pg0/ cs0 the pin function is switched as shown below according to the operating mode, bit pgnddr, and bit csne. operating mode 1, 2, 4, 5, 6 7 expe 01 csne 0 1 01 pgnddr 0101010101 pin function pgn input pin pgn output pin pgn input pin csn output pin pgn input pin pgn output pin pgn input pin pgn output pin pgn input pin csn output pin (n =1 or 0)
287 5.17 port h 5.17.1 overview port h is a 4-bit i/o port. port h pins also function as bus control signal output pins ( cs7 to cs4 and oe ) and interrupt signal input pins ( irq7 and irq6 ). figure 5.16 shows the port h pin configuration. ph3 / cs7 / oe / irq7 ph2 / cs6 / irq6 ph1 / cs5 ph0 / cs4 port h port h pins pin functions in modes 1, 2, 4, 5, 6, and 7 ph3 (i/o) / cs7 (output) / oe (output) / irq7 (input) ph2 (i/o) / cs6 (output) / irq6 (input) ph1 (i/o) / cs5 (output) ph0 (i/o) / cs4 (output) figure 5.16 port h pin functions 5.17.2 register configuration table 5.36 shows the port h register configuration. table 5.36 port h registers name abbreviation r/w initial value address * port h data direction register phddr w h'00 h'ff74 port h data register phdr r/w h'00 h'ff72 port h register porth r undefined h'ff70 port function control register 0 pfcr0 r/w h'ff h'fe32 port function control register 2 pfcr2 r/w h'0e h'fe34 note: * lower 16 bits of the address.
288 port h data direction register (phddr) bit 76543210 ph3ddr ph2ddr ph1ddr ph0ddr initial value 00000000 read/write wwww phddr is a 4-bit write-only register, the individual bits of which specify input or output for the pins of port h. phddr cannot be read; if it is, an undefined value will be read. phddr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. the ope bit in sbycr is used to select whether the bus control output pins retain their output state or become high-impedance when a transition is made to software standby mode. ? modes 1, 2, 4, 5, and 6 when the oe output enable bit (oee) and oe output select bit (oes) are set to 1, pin ph3 functions as the oe output pin. otherwise, when bit cs7e is set to 1, pin ph3 functions as a cs output pin when the corresponding phddr bit is set to 1, and as an input port when the bit is cleared to 0. when bit cs7e is cleared to 0, pin ph3 is an i/o port, and its function can be switched with phddr. when the cs output enable bits (cs6e to cs4e) are set to 1, pins ph2 to ph0 function as cs output pins when the corresponding phddr bit is set to 1, and as i/o ports when the bit is cleared to 0. when cs6e to cs4e are cleared to 0, pins ph2 to ph0 are i/o ports, and their functions can be switched with phddr. ? mode 7 (when bit expe is set to 1 in syscr) when the oe output enable bit (oee) and oe output select bit (oes) are set to 1, pin ph3 functions as the oe output pin. otherwise, when bit cs7e is set to 1, pin ph3 functions as a cs output pin when the corresponding phddr bit is set to 1, and as an input port when the bit is cleared to 0. when bit cs7e is cleared to 0, pin ph3 is an i/o port, and their functions can be switched with phddr. when the cs output enable bits (cs6e to cs4e) are set to 1, pins ph2 to ph0 function as cs output pins when the corresponding phddr bit is set to 1, and as input ports when the bit is cleared to 0. when cs6e to cs4e are cleared to 0, pins ph2 to ph0 are i/o ports, and their functions can be switched with phddr. ? mode 7 (when bit expe is cleared to 0 in syscr) pins ph3 to ph0 are i/o ports, and their functions can be switched with phddr.
289 port h data register (phdr) bit 76543210 ph3dr ph2dr ph1dr ph0dr initial value 00000000 read/write r/w r/w r/w r/w phdr is a 4-bit readable/writable register that stores output data for the port h pins (ph3 to ph0). bits 7 to 4 are reserved; they are always read as 0 and cannot be modified. phdr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. port h register (porth) bit 76543210 ph3 ph2 ph1 ph0 initial value undefined undefined undefined undefined * * * * read/write rrrr note: * determined by the state of pins ph3 to ph0. porth is a 4-bit read-only register that shows the pin states. porth cannot be written to; writing of output data for the port h pins (ph3 to ph0) must always be performed on phdr. bits 7 to 4 are reserved; if read they will return an undefined value. if a port h read is performed while phddr bits are set to 1, the phdr values are read. if a port h read is performed while phddr bits are cleared to 0, the pin states are read. after a reset and in hardware standby mode, porth contents are determined by the pin states, as phddr and phdr are initialized. porth retains its prior state in software standby mode. port function control register 0 (pfcr0) bit 76543210 cs7e cs6e cs5e cs4e cs3e cs2e cs1e cs0e initial value 11111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w pfcr0 is an 8-bit readable/writable register that performs i/o port control. pfcr0 is initialized to h'ff by a reset and in hardware standby mode. it retains its prior state in software standby mode.
290 bits 7 to 0?s7 to cs0 enable (cs7e to cs0e): these bits enable or disable the corresponding csn output. bit n csne description 0 pin is designated as i/o port and does not function as csn output pin 1 pin is designated as csn output pin (initial value) (n = 7 to 0) port function control register 2 (pfcr2) bit 76543210 asoe lwroe oes dmacs initial value 00001110 read/write r/w r/w r/w r/w pfcr2 is an 8-bit readable/writable register that performs i/o port control. pfcr2 is initialized to h'0e by a reset and in hardware standby mode. it retains its prior state in software standby mode. bits 7 to 4?eserved: these bits are always read as 0, and should only be written with 0. bit 1?e output select (oes): selects the oe output pin port when the oee bit is set to 1 in dramcr (enabling oe output). bit 1 oes description 0 p35 is designated as oe output pin 1 ph5 is designated as oe output pin (initial value) 5.17.3 pin functions port h pins also function as bus control signal output pins ( cs7 to cs4 and oe ) and interrupt signal input pins ( irq7 and irq6 ). port h pin functions are shown in table 5.37.
291 table 5.37 port h pin functions pin selection method and pin functions ph3/ cs7 / oe / irq7 the pin function is switched as shown below according to the operating mode, bit expe, bit oee, bit oes, bit cs7e, and bit ph3ddr. operating mode 1, 2, 4, 5, 6 7 expe 01 oee 0 1 01 oes 01 01 cs7e 0 1 0 1 01 01 ph3ddr 0 1 0101 01 0 1010 1010 1 pin function ph3 input pin ph3 output pin ph3 input pin cs7 output pin ph3 input pin ph3 output pin ph3 input pin cs7 output pin oe output pin ph3 input pin ph3 output pin ph3 input pin ph3 output pin ph3 input pin cs7 output pin ph3 input pin ph3 output pin ph3 input pin cs7 output pin oe output pin irq7 interrupt input pin * note: * irq7 interrupt input pin when bit its7 is set to 1 in itsr. ph2/ cs6 / irq6 the pin function is switched as shown below according to the operating mode, bit cs6e, and bit ph2ddr. operating mode 1, 2, 4, 5, 6 7 expe 01 cs6e 0 1 01 ph2ddr 0101010101 pin function ph2 input pin ph2 output pin ph2 input pin cs6 output pin ph2 input pin ph2 output pin ph2 input pin ph2 output pin ph2 input pin cs6 output pin irq6 interrupt input pin * note: * irq6 interrupt input pin when bit its6 is set to 1 in itsr. ph1/ cs5 ph0/ cs4 the pin function is switched as shown below according to the operating mode, bit csne, bits rmts2 to rmts0, and bit phmddr. operating mode 1, 2, 4, 5, 6 7 expe 01 csne 0 1 01 rmts2 to rmts0 area n in dram space area n in normal space area n in dram space area n in normal space phmddr 0 1 010101 01 pin function phm input pin phm output pin rasn output pin phm input pin csn output pin phm input pin phm output pin phm input pin phm output pin rasn output pin phm input pin csn output pin (m = 2 or 1, n = 5 or 4)
292 5.18 pin functions 5.18.1 port states in each processing state table 5.38 i/o port states in each processing state port name pin name mcu operating mode reset hardware standby mode software standby mode bus-released state program execution state sleep mode port 1 1, 2, 4 to 7 t t keep keep i/o port port 2 1, 2, 4 to 7 t t keep keep i/o port p34 to p30 1, 2, 4 to 7 t t keep keep i/o port p35 1, 2, 4 to 7 t t [ oe output, ope = 0] t [ oe output, ope = 1] h [otherwise] keep [ oe output] t [otherwise] keep [ oe output] oe [otherwise] i/o port p47/da1 1, 2, 4 to 7 t t [daoe1 = 1] keep [daoe1 = 0] t keep input port p46/da0 1, 2, 4 to 7 t t [daoe0 = 1] keep [daoe0 = 0] t keep input port p45 to p40 1, 2, 4 to 7 t t t t input port p57/da3 1, 2, 4 to 7 t t [daoe3 = 1] keep [daoe3 = 0] t keep input port p56/da2 1, 2, 4 to 7 t t [daoe2 = 1] keep [daoe2 = 0] t keep input port p55, p54 1, 2, 4 to 7 t t t t input port p53 to p50 1, 2, 4 to 7 t t keep keep i/o port port 6 1, 2, 4 to 7 t t keep keep i/o port port 7 1, 2, 4 to 7 t t keep keep i/o port port 8 1, 2, 4 to 7 t t keep keep i/o port
293 port name pin name mcu operating mode reset hardware standby mode software standby mode bus-released state program execution state sleep mode pa7/a23 pa6/a22 pa5/a21 1, 2, 4 to 7 t t [address output, ope = 0] t [address output, ope = 1] keep [otherwise] keep [address output] t [otherwise] keep [address output] a23 to a21 [otherwise] i/o port pa4/a20 pa3/a19 pa2/a18 pa1/a17 1, 2, 5, 6 l t [ope = 0] t [ope = 1] keep t address output a20 to a16 pa0/a16 4, 7 t t [address output, ope = 0] t [address output, ope = 1] keep [otherwise] keep [address output] t [otherwise] keep [address output] a20 to a16 [otherwise] i/o port port b 1, 2, 5, 6 l t [ope = 0] t [ope = 1] keep t address output a15 to a8 4 t t [address output, ope = 0] t [address output, ope = 1] keep [otherwise] keep [address output] t [otherwise] keep [address output] a15 to a8 [otherwise] i/o port 7 t t [address output, ope = 0] t [address output, ope = 1] keep [otherwise] keep [address output] t [otherwise] keep [address output] a15 to a8 [otherwise] i/o port
294 port name pin name mcu operating mode reset hardware standby mode software standby mode bus-released state program execution state sleep mode port c 1, 2, 5, 6 l t [ope = 0] t [ope = 1] keep t address output a7 to a0 4 t t [address output, ope = 0] t [address output, ope = 1] keep [otherwise] keep [address output] t [otherwise] keep [address output] a7 to a0 [otherwise] i/o port 7 t t [address output, ope = 0] t [address output, ope = 1] keep [otherwise] keep [address output] t [otherwise] keep [address output] a7 to a0 [otherwise] i/o port port d 1, 2, 4 to 6 t t t t d15 to d8 7 t t [data bus] t [otherwise] keep [data bus] t [otherwise] keep [data bus] d15 to d8 [otherwise] i/o port port e 1, 2, 4 to 6 8-bit bus t t keep keep i/o port 16-bit bus t t t t d7 to d0 7 8-bit bus t t keep keep i/o port 16-bit bus t t [data bus] t [otherwise] keep [data bus] t [otherwise] keep [data bus] d7 to d0 [otherwise] i/o port pf7/ 1, 2, 4 to 6 clock output t [clock output] h [clock output] clock output [clock output] clock output 7 t [otherwise] keep [otherwise] keep [otherwise] input port pf6/ as 1, 2, 4 to 6 h t [ as output, ope = 0] t [ as output] t [ as output] as 7t [ as output, ope = 1] h [otherwise] keep [otherwise] keep [otherwise] i/o port
295 port name pin name mcu operating mode reset hardware standby mode software standby mode bus-released state program execution state sleep mode pf5/ rd pf4/ hwr 1, 2, 4 to 6 h t [ope = 0] t [ope = 1] h t rd , hwr 7t [ rd , hwr output, ope = 0] t [ rd , hwr output, ope = 1] h [otherwise] keep [ rd , hwr output] t [otherwise] keep [ rd , hwr output] rd , hwr [otherwise] i/o port pf3/ lwr 1, 2, 4 to 6 h t [ lwr output, ope = 0] t [ lwr output] t [ lwr output] lwr 7t [ lwr output, ope = 1] h [otherwise] keep [otherwise] keep [otherwise] i/o port pf2/ lcas 1, 2, 4 to 7 t t [ lcas output, ope = 0] t [ lcas output, ope = 1] h [otherwise] keep [ lcas output] t [otherwise] keep [ lcas output] lcas [otherwise] i/o port pf1/ ucas 1, 2, 4 to 7 t t [ ucas output, ope = 0] t [ ucas output, ope = 1] h [otherwise] keep [ ucas output] t [otherwise] keep [ ucas output] ucas [otherwise] i/o port pf0/ wait 1, 2, 4 to 7 t t [ wait input] t [otherwise] keep [ wait input] t [otherwise] keep [ wait input] wait [otherwise] i/o port pg6/ breq 1, 2, 4 to 7 t t [ breq input] t [otherwise] keep breq input breq [ breq input] breq [otherwise] i/o port pg5/ back 1, 2, 4 to 7 t t [ back output] back [otherwise] keep back [back output] back [otherwise] i/o port
296 port name pin name mcu operating mode reset hardware standby mode software standby mode bus-released state program execution state sleep mode pg4/ breqo 1, 2, 4 to 7 t t [ breqo output] breqo [otherwise] keep breqo output breqo [otherwise] keep [ breqo output] breqo [otherwise] i/o port pg3/ cs3 pg2/ cs2 pg1/ cs1 1, 2, 4 to 7 t t [ cs output, ope = 0] t [ cs output, ope = 1] h [otherwise] keep [ cs output] t [otherwise] keep [ cs output] cs [otherwise] i/o port pg0/ cs0 1, 2, 5, 6 h t [ cs output, ope = 0] t [ cs output] t [ cs output] cs 4, 7 t [ cs output, ope = 1] h [otherwise] keep [otherwise] keep [otherwise] i/o port ph3/ oe / cs7 1, 2, 4 to 7 t t [ oe output, ope = 0] t [ oe output, ope = 1] h [ cs output, ope = 0] t [ cs output, ope = 1] h [otherwise] keep [ oe output] t [ cs output] t [otherwise] keep [ oe output] oe [ cs output] cs [otherwise] i/o port ph2/ cs6 ph1/ cs5 ph0/ cs4 1, 2, 4 to 7 t t [ cs output, ope = 0] t [ cs output, ope = 1] h [otherwise] keep [ cs output] t [otherwise] keep [ cs output] cs [otherwise] i/o port legend l: low level keep: input port becomes high-impedance, output port retains state ope: output port enable h: high level t: high impedance ddr data direction register note: * shows the state after completion of the executing bus cycle.
297 5.19 i/o port block diagrams 5.19.1 port 1 * r p1nddr c qd reset wddr1 r p1ndr c qd reset wdr1 internal data bus ppg module pulse output enable pulse output tpu module output compare output/ pwm output enable output compare output/ pwm output input capture input wddr1: write to p1ddr wdr1: write to p1dr rpor1: read port 1 rdr1: read p1dr n = 0, 1, 4 note: * output enable signal priority order: tpu > ppg > dr p1n rdr1 rpor1 figure 5.17 port 1 block diagram (a) (pins p10, p11, and p14)
298 * r p1nddr c qd reset wddr1 r p1ndr c qd reset wdr1 ppg module pulse output enable pulse output tpu module output compare output/ pwm output enable output compare output/ pwm output input capture input external clock input wddr1: write to p1ddr wdr1: write to p1dr rpor1: read port 1 rdr1: read p1dr n = 2, 3, 5 note: * output enable signal priority order: tpu > ppg > dr p1n rdr1 rpor1 internal data bus figure 5.18 port 1 block diagram (b) (pins p12, p13, and p15)
299 rpor1 * r p16ddr c qd reset wddr1 r p16dr c qd reset wdr1 system controller expe exdmac module edreq acknowledge enable edreq acknowledge output tpu module output compare output/ pwm output enable output compare output/ pwm output input capture input ppg module pulse output enable pulse output p16 rdr1 modes 1, 2, 4, 5, 6 mode 7 internal data bus wddr1: write to p1ddr wdr1: write to p1dr rpor1: read port 1 rdr1: read p1dr note: * output enable signal priority order: modes 1, 2, 4, 5, 6, 7 (expe = 1) exdmac > tpu > ppg > dr mode 7 (expe = 0) tpu > ppg > dr figure 5.19 port 1 block diagram (c) (pin p16)
300 rpor1 * r p17ddr c qd reset wddr1 r p17dr c qd reset wdr1 system controller expe exdmac module edreq acknowledge enable edreq acknowledge output tpu module output compare output/ pwm output enable output compare output/ pwm output external clock input input capture input ppg module pulse output enable pulse output p17 rdr1 modes 1, 2, 4, 5, 6 mode 7 internal data bus wddr1: write to p1ddr wdr1: write to p1dr rpor1: read port 1 rdr1: read p1dr note: * output enable signal priority order: modes 1, 2, 4, 5, 6, 7 (expe = 1) exdmac > tpu > ppg > dr mode 7 (expe = 0) tpu > ppg > dr figure 5.20 port 1 block diagram (d) (pin p17)
301 5.19.2 port 2 * r p2nddr c qd reset wddr2 r p2ndr c qd reset wdr2 ppg module pulse output enable pulse output tpu module interrupt controller output compare output/ pwm output enable output compare output/ pwm output itsm irqmb input capture input p2n rdr2 rpor2 internal data bus wddr2: write to p2ddr wdr2: write to p2dr rpor2: read port 2 rdr2: read p2dr n = 0 to 5 m = 8 to 13 note: * output enable signal priority order: tpu > ppg > dr figure 5.21 port 2 block diagram (a) (pins p20 to p25)
302 rpor2 * r p2nddr c qd reset wddr2 r p2ndr c qd reset wdr2 system controller expe exdmac module edreq acknowledge enable edreq acknowledge output tpu module output compare output/ pwm output enable output compare output/ pwm output input capture input ppg module pulse output enable pulse output p2n rdr2 modes 1, 2, 4, 5, 6 mode 7 interrupt controller itsm irqm internal data bus wddr2: write to p2ddr wdr2: write to p2dr rpor2: read port 2 rdr2: read p2dr n = 6 or 7 m = 14 or 15 note: * output enable signal priority order: modes 1, 2, 4, 5, 6, 7 (expe = 1) exdmac > tpu > ppg > dr mode 7 (expe = 0) tpu > ppg > dr figure 5.22 port 2 block diagram (b) (pins p26 and p27)
303 5.19.3 port 3 reset wddr3 reset wdr3 p3n rdr3 rodr3 rpor3 reset wodr3 sci module serial transmit enable serial transmit data wddr3: write to p3ddr wdr3: write to p3dr wodr3: write to p3odr rpor3: read port 3 rdr3: read p3dr rodr3: read p3odr n = 0 or 1 notes: 1. output enable signal 2. open drain control signal priority order: sci > dr * 1 * 2 r p3nddr c qd r p3ndr c qd r p3nodr c qd internal data bus figure 5.23 port 3 block diagram (a) (pins p30 and p31)
304 reset wddr3 reset wdr3 p3n rdr3 rodr3 rpor3 reset wodr3 sci module serial receive data enable serial receive data * 1 * 2 wddr3: write to p3ddr wdr3: write to p3dr wodr3: write to p3odr rpor3: read port 3 rdr3: read p3dr rodr3: read p3odr n = 2 or 3 notes: 1. output enable signal 2. open drain control signal r p3nddr c qd r p3ndr c qd r p3nodr c qd internal data bus figure 5.24 port 3 block diagram (b) (pins p32 and p33)
305 reset wddr3 reset wdr3 p34 rdr3 rodr3 rpor3 reset wodr3 sci module * 1 * 2 serial clock output enable serial clock output serial clock input enable serial clock input wddr3: write to p3ddr wdr3: write to p3dr wodr3: write to p3odr rpor3: read port 3 rdr3: read p3dr rodr3: read p3odr notes: 1. output enable signal 2. open drain control signal priority order: sci > dr r p34ddr c qd r p34dr c qd r p34odr c qd internal data bus figure 5.25 port 3 block diagram (c) (pin p34)
306 reset wddr3 reset wdr3 p35 rdr3 rpor3 rpor3 reset wodr3 rpfcr2 reset wpfcr2 sci module * 1 * 2 system controller expe serial clock output enable serial clock output serial clock input enable serial clock input bus controller oeb oee mode 7 r p35ddr c qd r p35dr c qd r p35odr c qd r qd c oes pfcr2 wddr3: write to p3ddr wdr3: write to p3dr wodr3: write to p3odr rpor3: read port 3 rdr3: read p3dr rodr3: read p3odr internal data bus modes 1, 2, 4, 5, 6 notes: 1. output enable signal 2. priority order: modes 1, 2, 4, 5, 6, 7 (expe = 1) oe > sci > dr mode 7 (expe = 0) sci > dr figure 5.26 port 3 block diagram (d) (pin p35)
307 5.19.4 port 4 p4n rpor4 a/d converter module analog input internal data bus rpor4: read port 4 n = 0 to 5 figure 5.27 port 4 block diagram (a) (pins p40 to p45) rpor4: read port 4 n = 6 or 7 p4n rpor4 a/d converter module analog input d/a converter module output enable analog output internal data bus figure 5.28 port 4 block diagram (b) (pins p46 and p47)
308 5.19.5 port 5 reset wddr5 reset wdr5 p50 rdr5 rpor5 sci module serial transmit enable serial transmit data interrupt controller its0 irq0 wddr5: write to p5ddr wdr5: write to p5dr rpor5: read port 5 rdr5: read p5dr note: * output enable signal priority order: sci > dr * r p50ddr c qd r p50dr c qd internal data bus figure 5.29 port 5 block diagram (a) (pin p50)
309 reset wddr5 reset wdr5 p51 rdr5 rpor5 * sci module serial receive data enable serial receive data interrupt controller its0 irq1 wddr5: write to p5ddr wdr5: write to p5dr rpor5: read port 5 rdr5: read p5dr note: * output enable signal r p51ddr c qd r p51ddr c qd internal data bus figure 5.30 port 5 block diagram (b) (pin p51)
310 reset wddr5 reset wdr5 p52 rdr5 rpor5 * sci module serial clock output enable serial clock output serial clock input enable serial clock input interrupt controller its2 irq2 wddr5: write to p5ddr wdr5: write to p5dr rpor5: read port 5 rdr5: read p5dr note: * output enable signal priority order: sci > dr r p52ddr c qd r p52dr c qd internal data bus figure 5.31 port 5 block diagram (c) (pin p52)
311 reset wddr5 reset wdr5 p53 rdr5 rpor5 interrupt controller its3 irq3 a/d converter a/d conversion external trigger input * wddr5: write to p5ddr wdr5: write to p5dr rpor5: read port 5 rdr5: read p5dr note: * output enable signal r p53ddr c qd r p53dr c qd internal data bus figure 5.32 port 5 block diagram (d) (pin p53)
312 p5n rpor5 a/d converter module analog input interrupt controller irqn itsn internal data bus rpor5: read port 5 n = 4 or 5 figure 5.33 port 5 block diagram (e) (pins p54 and p55) p5n rpor5 a/d converter module analog input interrupt controller irqn itsn d/a converter module output enable analog output rpor5: read port 5 n = 6 or 7 internal data bus figure 5.34 port 5 block diagram (f) (pins p56 and p57)
313 5.19.6 port 6 reset wddr6 reset wdr6 p6n rdr6 rpor6 interrupt controller itsm irqm * wddr6: write to p6ddr wdr6: write to p6dr rpor6: read port 6 rdr6: read p6dr n = 0 or 1 m = 8 or 9 note: * output enable signal dma controller dma request input 8-bit timer module counter external reset input r p6nddr c qd r p6ndr c qd internal data bus figure 5.35 port 6 block diagram (a) (pins p60 and p61)
314 reset wddr6 reset wdr6 p6n rdr6 rpfcr2 rpor6 reset wpfcr2 dma controller * dma transfer end enable dma transfer end interrupt controller itsm irqm 8-bit timer module counter external clock input wddr6: write to p6ddr wdr6: write to p6dr wpfcr2: write to pfcr2 rpor6: read port 6 rdr6: read p6dr rpfcr2: read pfcr2 n = 2 or 3 m = 10 or 11 r p6nddr c qd r p6ndr c qd r qd c dmacs pfcr2 internal data bus note: * output enable signal priority order: dmacs = 0 dmac > dr dmacs = 1 dr figure 5.36 port 6 block diagram (b) (pins p62 and p63)
315 reset wddr6 reset wdr6 p6n rdr6 rpfcr2 rpor6 reset wpfcr2 dma controller * dma transfer acknowledge enable dma transfer acknowledge 8-bit timer module compare match output enable compare match output interrupt controller itsm irqm wddr6: write to p6ddr wdr6: write to p6dr wpfcr2: write to pfcr2 rpor6: read port 6 rdr6: read p6dr rpfcr2: read pfcr2 n = 4 or 5 m = 12 or 13 r p6nddr c qd r p6ndr c qd r qd c dmacs pfcr2 internal data bus note: * output enable signal priority order: dmacs = 0 dmac > tmr > dr dmacs = 1 tmr > dr figure 5.37 port 6 block diagram (c) (pins p64 and p65)
316 5.19.7 port 7 reset wddr7 reset wdr7 p7n rdr7 rpor7 * wddr7: write to p7ddr wdr7: write to p7dr rpor7: read port 7 rdr7: read p7dr n = 0 or 1 note: * output enable signal dma controller dma request input exdma controller exdma request input r p7nddr c qd r p7ndr c qd internal data bus figure 5.38 port 7 block diagram (a) (pins p70 and p71)
317 reset wddr7 reset wdr7 p7n rdr7 rpfcr2 rpor7 reset wpfcr2 dma controller * dma transfer end enable dma transfer end exdma controller exdma transfer end enable exdma transfer end modes 1, 2, 4, 5, 6 mode 7 system controller expe wddr7: write to p7ddr wdr7: write to p7dr wpfcr2: write to pfcr2 rpor7: read port 7 rdr7: read p7dr rpfcr2: read pfcr2 n = 2 or 3 r p7nddr c qd r p7ndr c qd r qd c dmacs pfcr2 internal data bus note: * output enable signal priority order: modes 1, 2, 4, 5, 6, 7 (expe = 1) mode 7 (expe = 1) dmacs = 1 dmacs = 1 exdmac > dmac > dr dmac > dr dmacs = 0 dmacs = 0 exdmac > dr dr figure 5.39 port 7 block diagram (b) (pins p72 and p73)
318 reset wddr7 reset wdr7 p7n rdr7 rpfcr2 rpor7 reset wpfcr2 dma controller * dma transfer acknowledge enable dma transfer acknowledge exdma controller exdma transfer acknowledge enable exdma transfer acknowledge modes 1, 2, 4, 5, 6 mode 7 system controller expe wddr7: write to p7ddr wdr7: write to p7dr wpfcr2: write to pfcr2 rpor7: read port 7 rdr7: read p7dr rpfcr2: read pfcr2 n = 4 or 5 r p7nddr c qd r p7ndr c qd r qd c dmacs pfcr2 internal data bus note: * output enable signal priority order: modes 1, 2, 4, 5, 6, 7 (expe = 1) mode 7 (expe = 1) dmacs = 1 dmacs = 1 exdmac > dmac > dr dmac > dr dmacs = 0 dmacs = 0 exdmac > dr dr figure 5.40 port 7 block diagram (c) (pins p74 and p75)
319 5.19.8 port 8 r p8nddr c qd reset wddr8 reset wdr8 r p8ndr c qd p8n rdr8 rpor8 interrupt controller itsn irqn * wddr8: write to p8ddr wdr8: write to p8dr rpor8: read port 8 rdr8: read p8dr n = 0 or 1 note: * output enable signal exdma controller exdma request input internal data bus figure 5.41 port 8 block diagram (a) (pins p80 and p81)
320 reset wddr8 reset wdr8 p8n rdr8 rpor8 * exdma controller exdma transfer end enable exdma transfer end mode 7 modes 1, 2, 4, 5, 6 system controller expe wddr8: write to p8ddr wdr8: write to p8dr rpor8: read port 8 rdr8: read p8dr n = 2 or 3 interrupt controller itsn irqn r p8nddr c qd r p8ndr c qd internal data bus note: * output enable signal priority order: modes 1, 2, 4, 5, 6, 7 (expe = 1) exdmac > dr mode 7 (expe = 0) dr figure 5.42 port 8 block diagram (b) (pins p82 and p83)
321 reset wddr8 reset wdr8 p8n rdr8 rpor8 * exdma controller exdma transfer acknowledge exdma transfer acknowledge enable mode 7 modes 1, 2, 4, 5, 6 system controller expe wddr8: write to p8ddr wdr8: write to p8dr rpor8: read port 8 rdr8: read p8dr n = 4 or 5 interrupt controller itsn irqn r p8nddr c qd r p8ndr c qd internal data bus note: * output enable signal priority order: modes 1, 2, 4, 5, 6, 7 (expe = 1) exdmac > dr mode 7 (expe = 0) dr figure 5.43 port 8 block diagram (c) (pins p84 and p85)
322 5.19.9 port a pan r panpcr c qd reset mode 4 mode 4 mode 7 mode 7 wpcra s ame pfcr1 c qd set wpfcr1 rpcra rpfcr1 r panddr c qd reset wddra r pandr c qd reset wdra r panodr c qd reset wodra modes 1, 2, 5, 6 rdra rpora rodra system controller expe wddra: write to paddr wdra: write to padr wodra: write to paodr wpcra: write to papcr wpfcr1: write to pfcr1 n = 0, 1, 2, 3, 4 m = 16, 17, 18, 19, 20 rpora: read port a rdra: read padr rodra: read paodr rpcra: read papcr rpfcr1: read pfcr1 notes: 1. output enable signal 2. open drain control signal * 1 * 2 internal data bus internal address bus modes 1, 2, 5, 6 figure 5.44 port a block diagram (a) (pins pa0 to pa4)
323 pan r panpcr c qd reset modes 1, 2, 4, 5, 6 mode 7 wpcra s ame pfcr1 c qd set wpfcr1 rpcra rpfcr1 r panddr c qd reset wddra r pandr c qd reset wdra r panodr c qd reset wodra rdra rpora rodra wddra: write to paddr wdra: write to padr wodra: write to paodr wpcra: write to papcr wpfcr1: write to pfcr1 n = 5, 6, 7 m = 21, 22, 23 * 1 * 2 system controller expe internal data bus internal address bus rpora: read port a rdra: read padr rodra: read paodr rpcra: read papcr rpfcr1: read pfcr1 notes: 1. output enable signal 2. open drain control signal figure 5.45 port a block diagram (b) (pins pa5 to pa7)
324 5.19.10 port b pbn r pbnpcr c qd reset wpcrb rpcrb r pbnddr c qd reset wddrb r pbndr c qd reset wdrb rdrb rporb wddrb: write to pbddr wdrb: write to pbdr wpcrb: write to pbpcr rporb: read port b rdrb: read pbdr rpcrb: read pbpcr n = 0 to 7 note: * output enable signal * mode 4 mode 7 mode 4 mode 7 modes 1, 2, 5, 6 system controller expe internal data bus internal address bus figure 5.46 port b block diagram (pins pbn)
325 5.19.11 port c pcn r pcnpcr c qd reset wpcrc rpcrc r pcnddr c qd reset wddrc r pcndr c qd reset wdrc rdrc rporc wddrc: write to pcddr wdrc: write to pcdr wpcrc: write to pcpcr rporc: read port c rdrc: read pcdr rpcrc: read pcpcr n = 0 to 7 note: * output enable signal * mode 4 mode 7 mode 4 mode 7 modes 1, 2, 5, 6 system controller expe internal data bus internal address bus figure 5.47 port c block diagram (pins pcn)
326 5.19.12 port d pdn r pdnpcr c qd reset wpcrd rpcrd r pdnddr c qd reset wddrd pdndr c qd reset wdrd rdrd rpord wddrd: write to pdddr wdrd: write to pddr wpcrd: write to pdpcr rpord: read port d rdrd: read pddr rpcrd: read pdpcr n = 0 to 7 note: * output enable signal * mode 7 modes 1, 2, 4, 5, 6 external data upper read external data lower read mode 7 external data upper write external data lower write system controller expe r internal upper data bus internal lower data bus figure 5.48 port d block diagram (pins pdn)
327 5.19.13 port e pen r penpcr c qd reset all areas 8-bit access space external data write modes 1, 2, 4, 5, 6 mode 7 all areas 8-bit access space mode 7 wpcre rpcre r penddr c qd reset wddre pendr c qd reset wdre rdre rpore wddre: write to peddr wdre: write to pedr wpcre: write to pepcr rpore: read port e rdre: read pedr rpcre: read pepcr n = 0 to 7 note: * output enable signal * external data lower read r system controller expe internal upper data bus internal lower data bus figure 5.49 port e block diagram (pins pen)
328 5.19.14 port f pf0 r pf0ddr c qd reset wddrf pf0dr c qd reset wdrf rdrf rporf system controller expe bus controller waite wait input * modes 1, 2, 4, 5, 6 mode 7 wddrf: write to pfddr wdrf: write to pfdr rporf: read port f rdrf: read pfdr note: * output enable signal r internal data bus figure 5.50 port f block diagram (a) (pin pf0)
329 pf1 r pf1ddr c qd reset wddrf pf1dr c qd reset dram space modes 1, 2, 4, 5, 6 mode 7 wdrf rdrf rporf expe ucas output wddrf: write to pfddr wdrf: write to pfdr rporf: read port f rdrf: read pfdr note: * output enable signal * r its14 irq14 input system controller bus controller interrupt controller internal data bus figure 5.51 port f block diagram (b) (pin pf1)
330 pf2 r pf2ddr c qd reset wddrf pf2dr c qd reset any dram space area is 16-bit access space modes 1, 2, 4, 5, 6 mode 7 wdrf rdrf rporf expe wddrf: write to pfddr wdrf: write to pfdr rporf: read port f rdrf: read pfdr note: * output enable signal * r its15 lcas output irq15 input system controller bus controller interrupt controller internal data bus figure 5.52 port f block diagram (c) (pin pf2)
331 pf3 r pf3ddr c qd reset wddrf pf3dr c qd reset wdrf rdrf rporf wddrf: write to pfddr wdrf: write to pfdr wpfcr2: write to pfcr2 rporf: read port f rdrf: read pfdr rpfcr2: read pfcr2 note: * output enable signal * r lwroe pfcr2 c qd set wpfcr2 s rpfcr2 expe lwr output system controller bus controller modes 1, 2, 4, 5, 6 mode 7 internal data bus figure 5.53 port f block diagram (d) (pin pf3)
332 reset wddrf reset wdrf pf4 rdrf rporf * wddrf: write to pfddr wdrf: write to pfdr rporf: read port f rdrf: read pfdr note: * output enable signal modes 1, 2, 4, 5, 6 mode 7 mode 7 modes 1, 2, 4, 5, 6 mode 7 expe hwr output system controller bus controller r pf4ddr c qd r pf4dr c qd internal data bus figure 5.54 port f block diagram (e) (pin pf4)
333 reset wddrf reset wdrf pf5 rdrf rporf * wddrf: write to pfddr wdrf: write to pfdr rporf: read port f rdrf: read pfdr note: * output enable signal modes 1, 2, 4, 5, 6 mode 7 mode 7 modes 1, 2, 4, 5, 6 mode 7 expe rd output system controller bus controller r pf5ddr c qd r pf5dr c qd internal data bus figure 5.55 port f block diagram (f) (pin pf5)
334 pf6 r pf6ddr c qd reset wddrf pf6dr c qd reset wdrf rdrf rporf wddrf: write to pfddr wdrf: write to pfdr wpfcr2: write to pfcr2 rporf: read port f rdrf: read pfdr rpfcr2: read pfcr2 note: * output enable signal * r asoe pfcr2 c qd set wpfcr2 s rpfcr2 expe as output system controller bus controller modes 1, 2, 4, 5, 6 mode 7 internal data bus figure 5.56 port f block diagram (g) (pin pf6)
335 wddrf reset wdrf pf7 rdrf rporf * wddrf: write to pfddr wdrf: write to pfdr rporf: read port f rdrf: read pfdr note: * output enable signal r s pf7ddr c qd modes 1, 2, 4, 5, 6 set mode 7 reset r pf7dr c qd internal data bus figure 5.57 port f block diagram (h) (pin pf7)
336 5.19.15 port g rporg * r s pg0ddr c qd modes 1, 2, 5, 6 set modes 4, 7 reset wddrg s pfcr0 cs0e c qd set wpfcr0 pg0 rdrg rpfcr0 cs wddrg: write to pgddr wdrg: write to pgdr wpfcr0: write to pfcr0 rporg: read port g rdrg: read pgdr rpfcr0: read pfcr0 note: * output enable signal modes 1, 2, 4, 5, 6 mode 7 expe cs system controller bus controller r pg0dr c qd reset wdrg internal data bus figure 5.58 port g block diagram (a) (pin pg0)
337 rporg * pg0ddr c qd wddrg s pfcr0 csne c qd set wpfcr0 pgn rdrg rpfcr0 cs wddrg: write to pgddr wdrg: write to pgdr wpfcr0: write to pfcr0 rporg: read port g rdrg: read pgdr rpfcr0: read pfcr0 n = 1 to 3 note: * output enable signal modes 1, 2, 4, 5, 6 mode 7 expe cs system controller bus controller r r pgndr c qd reset reset wdrg internal data bus figure 5.59 port g block diagram (b) (pins pg1 to pg3)
338 pg4 r pg4ddr c qd reset wddrg pg4dr c qd reset wdrg rdrg rporg brle breqoe breqo wddrg: write to pgddr wdrg: write to pgdr rporg: read port g rdrg: read pgdr note: * output enable signal * r modes 1, 2, 4, 5, 6 mode 7 expe system controller bus controller internal data bus figure 5.60 port g block diagram (c) (pin pg4)
339 pg5 r pg5ddr c qd reset wddrg pg5dr c qd reset wdrg rdrg rporg * r modes 1, 2, 4, 5, 6 mode 7 expe system controller brle back bus controller wddrg: write to pgddr wdrg: write to pgdr rporg: read port g rdrg: read pgdr note: * output enable signal internal data bus figure 5.61 port g block diagram (d) (pin pg5)
340 pg6 r pg6ddr c qd reset wddrg pg6dr c qd reset wdrg rdrg rporg * modes 1, 2, 4, 5, 6 mode 7 brle breq input expe system controller bus controller wddrg: write to pgddr wdrg: write to pgdr rporg: read port g rdrg: read pgdr note: * output enable signal internal data bus r figure 5.62 port g block diagram (e) (pin pg6)
341 5.19.16 port h phn r phnddr c qd reset wddrh csme pfcr0 c qd set wpfcr0 rdrh rporh * rpfcr0 s phndr c qd reset wdrh r expe system controller cs bus controller wddrh: write to phddr wdrh: write to phdr wpfcr0: write to pfcr0 rporh: read port h rdrh: read phdr rpfcr0: read pfcr0 n = 0 or 1 m = 4 or 5 note: * output enable signal modes 1, 2, 4, 5, 6 mode 7 internal data bus figure 5.63 port h block diagram (a) (pins ph0 and ph1)
342 ph2 r ph2ddr c qd reset wddrh cs6e pfcr0 c qd set wpfcr0 rdrh rporh its6 irq6 input * rpfcr0 s ph2dr c qd reset wdrh r expe system controller cs bus controller interrupt controller modes 1, 2, 4, 5, 6 mode 7 wddrh: write to phddr wdrh: write to phdr wpfcr0: write to pfcr0 rporh: read port h rdrh: read phdr rpfcr0: read pfcr0 note: * output enable signal internal data bus figure 5.64 port h block diagram (b) (pin ph2)
343 ph3 r ph3dr c qd reset wdrh s pfcr2 oes c qd set wpfcr2 r ph3dr c qd reset wdrh s cs7e pfcr0 c qd set wpfcr0 rdrh rpfcr2 rpfcr0 rporh cs oe oee * modes 1, 2, 4, 5, 6 modes 1, 2, 4, 5, 6 mode 7 mode 7 expe system controller bus controller its7 irq7 input interrupt controller wddrh: write to phddr wdrh: write to phdr wpfcr0: write to pfcr0 rporh: read port h rdrh: read phdr rpfcr0: read pfcr0 internal data bus note: * output enable signal figure 5.65 port h block diagram (c) (pin ph3)
344
345 section 6 supporting module block diagrams 6.1 interrupt controller 6.1.1 features ? selection of two interrupt control modes ? eight priority levels can be set for each module with ipr ? independent vector addresses ? 17 external interrupt pins (nmi, irq15 to irq0 ) ? dtc and dmac activation control 6.1.2 block diagram intcr nmi input irq input internal interrupt source swdtend to tei intm1 intm0 nmieg nmi input unit irq input unit isr iscr itsr ier ipr interrupt controller priority determination interrupt request vector number i i2 to i0 ccr exr cpu legend iscr: irq sense control register ier: irq enable register isr: irq status register ipr: interrupt priority register intcr: interrupt control register itsr: irq pin select register figure 6.1 block diagram of interrupt controller
346 6.1.3 pins table 6.1 interrupt controller pins name abbreviation i/o function nonmaskable interrupt nmi input nonmaskable external interrupt; rising or falling edge can be selected external interrupt requests 15 to 0 irq15 to irq0 input maskable external interrupts; rising, falling, or both edges, or level sensing, can be selected 6.2 dma controller 6.2.1 features ? selection of short address mode or full address mode ? 16-mbyte address space can be specified directly ? byte or word can be set as the transfer unit ? activation sources: internal interrupt, external request, auto-request (depending on transfer mode) ? module stop mode can be set
347 6.2.2 block diagram internal address bus address buffer processor internal interrupts tgi0a tgi1a tgi2a tgi3a tgi4a tgi5a txi0 rxi0 txi1 rxi1 adi external pins dreq0 dreq1 tend0 tend1 dack0 dack1 interrupt signals dend0a dend0b dend1a dend1b control logic dmawer dmacr1b dmacr1a dmacr0b dmacr0a dmatcr dmabcr data buffer internal data bus mar0a ioar0a etcr0a mar0b ioar0b etcr0b mar1a ioar1a etcr1a mar1b ioar1b etcr1b legend dmawer: dma write enable register dmatcr: dma terminal control register dmabcr: dma band control register (for all channels) dmacr: dma control register mar: memory address register ioar: i/o address register etcr: execute transfer count register module data bus channel 0 channel 1 channel 0a channel 0b channel 1a channel 1b figure 6.2 block diagram of dmac
348 6.2.3 pins table 6.2 dmac pins channel name abbreviation i/o function 0 dma request 0 dreq0 input dmac channel 0 external request dma transfer acknowledge 0 dack0 output dmac channel 0 single address transfer acknowledge dma transfer end 0 tend0 output dmac channel 0 transfer end 1 dma request 1 dreq1 input dmac channel 1 external request dma transfer acknowledge 1 dack1 output dmac channel 1 single address transfer acknowledge dma transfer end 1 tend1 output dmac channel 1 transfer end 6.3 data transfer controller 6.3.1 features ? transfer possible over any number of channels ? variety of transfer modes, including normal, repeat, and block transfer ? direct specification of 16-mbyte address space possible ? byte or word can be selected as the transfer unit ? a cpu interrupt can be requested for an interrupt that activates the dtc ? can be activated by software ? module stop mode can be set
349 6.3.2 block diagram dtc register information is located in on-chip ram*. as the dtc and on-chip ram (1-kbyte) are connected by a 32-bit bus, a 32-bit read or write of dtc register information can be executed in one state. note: * when the dtc is used, the rame bit must be set to 1 in syscr. internal address bus dtcera to dtcerh dtvecr interrupt controller dtc on-chip ram internal data bus dtc activa- tion request cpu interrupt request mra mrb cra crb dar sar interrupt request legend mra, mrb: dtc mode registers a and b cra, crb: dtc transfer count registers a and b sar: dtc source address register dar: dtc destination address register dtcera to dtcerh: dtc enable registers a to h dtvecr: dtc vector register control logic register information figure 6.3 block diagram of dtc
350 6.4 exdma controller (exdmac) 6.4.1 features ? four channels ? physical address space (16-mbyte flat external space) ? byte or word transfer data length can be selected ? maximum number of transfers: 16m (16,777,215)/infinite (free-running) ? selection of dual address mode or single address mode ? two kinds of exdmac transfer activation requests: external request and auto request ? cycle steal mode or burst mode can be selected as bus mode ? normal mode or block transfer mode can be selected as transfer mode
351 6.4.2 block diagram bus controller internal data bus interrupt request signals to cpu for individual channels external pins edmdrn edacrn edtcrn eddarn edsarn processor address buffer data buffer legend edsarn: exdma source address register eddarn: exdma destination address register edtcrn: exdma transfer count register edmdrn: exdma mode control register edacrn: exdma address control register edreqn : exdma transfer request edrakn : edreqn acknowledge etendn : exdma transfer end edackn : exdma transfer acknowledge n = 0 to 3 control logic module data bus edreqn edrakn etendn edackn figure 6.4 block diagram of exdmac
352 6.4.3 pins table 6.3 exdmac pins channel name abbreviation i/o function 0 exdma transfer request 0 edreq0 input exdmac channel 0 external request exdma transfer acknowledge 0 edack0 output exdmac channel 0 single address transfer acknowledge exdma transfer end 0 etend0 output exdmac channel 0 transfer end edreq0 acknowledge edrak0 output notification to external device of channel 0 external request acceptance and start of execution 1 exdma transfer request 1 edreq1 input exdmac channel 1 external request exdma transfer acknowledge 1 edack1 output exdmac channel 1 single address transfer acknowledge exdma transfer end 1 etend1 output exdmac channel 1 transfer end edreq1 acknowledge edrak1 output notification to external device of channel 1 external request acceptance and start of execution 2 exdma transfer request 2 edreq2 input exdmac channel 2 external request exdma transfer acknowledge 2 edack2 output exdmac channel 2 single address transfer acknowledge exdma transfer end 2 etend2 output exdmac channel 2 transfer end edreq2 acknowledge edrak2 output notification to external device of channel 2 external request acceptance and start of execution 3 exdma transfer request 3 edreq3 input exdmac channel 3 external request exdma transfer acknowledge 3 edack3 output exdmac channel 3 single address transfer acknowledge exdma transfer end 3 etend3 output exdmac channel 3 transfer end edreq3 acknowledge edrak3 output notification to external device of channel 3 external request acceptance and start of execution
353 6.5 16-bit timer pulse unit 6.5.1 features ? six 16-bit timer channels ? maximum 16 pulse inputs/outputs ? selection of 8 counter input clocks for each channel ? compare match, input capture, counter clear operation, synchronous operation, and pwm mode can be set for each channel ? buffer operation can be set for channels 0 and 3 ? phase counting mode can be set independently for each of channels 1, 2, 4, and 5 ? cascaded operation possible by connecting two 16-bit counter channels to form a 32-bit counter ? fast access via internal 16-bit bus ? programmable pulse generator (ppg) output trigger can be generated ? a/d converter conversion start trigger can be generated ? module stop mode can be set
354 6.5.2 block diagram channel 3 tmdr tiorl tsr tcr tiorh tier tgra tcnt tgrb tgrc tgrd channel 4 tmdr tsr tcr tior tier tgra tcnt tgrb channel 5 tmdr tsr tcr tior tier tgra tcnt tgrb control logic for channels 3 to 5 channel 2 tmdr tsr tcr tior tier tgra tcnt tgrb tgrc channel 1 tmdr tsr tcr tior tier tgra tcnt tgrb channel 0 tmdr tsr tcr tiorh tier control logic for channels 0 to 2 tgra tcnt tgrb tgrd bus interface common tsyr control logic tstr [input/output pins] tioca3 tiocb3 tiocc3 tiocd3 tioca4 tiocb4 tioca5 tiocb5 [clock input] ?1 ?4 ?16 ?64 ?256 ?1024 ?4096 tclka tclkb tclkc tclkd [input/output pins] tioca0 tiocb0 tiocc0 tiocd0 tioca1 tiocb1 tioca2 tiocb2 [interrupt request signals] channel 3: channel 4: channel 5: [interrupt request signals] channel 0: channel 1: channel 2: internal data bus a/d conversion start request signal ppg output trigger signal tiorl module data bus tgi3a tgi3b tgi3c tgi3d tci3v tgi4a tgi4b tci4v tci4u tgi5a tgi5b tci5v tci5u tgi0a tgi0b tgi0c tgi0d tci0v tgi1a tgi1b tci1v tci1u tgi2a tgi2b tci2v tci2u channel 3: channel 4: channel 5: internal clock: external clock: channel 0: channel 1: channel 2: legend tstr: timer start register tsyr: timer synchro register tcr: timer control register tmdr: timer mode register tior (h, l): timer i/o control registers (h, l) tier: timer interrupt enable register tsr: timer status register tgr (a, b, c, d): timer general registers (a, b, c, d) figure 6.5 block diagram of tpu
355 6.5.3 pins table 6.4 tpu pins channel name abbre- viation i/o function all clock input a tclka input external clock a input pin (channel 1 and 5 phase counting mode a-phase input) clock input b tclkb input external clock b input pin (channel 1 and 5 phase counting mode b-phase input) clock input c tclkc input external clock c input pin (channel 2 and 4 phase counting mode a-phase input) clock input d tclkd input external clock d input pin (channel 2 and 4 phase counting mode b-phase input) 0 input capture/out compare match a0 tioca0 i/o tgr0a input capture input/output compare output/pwm output pin input capture/out compare match b0 tiocb0 i/o tgr0b input capture input/output compare output/pwm output pin input capture/out compare match c0 tiocc0 i/o tgr0c input capture input/output compare output/pwm output pin input capture/out compare match d0 tiocd0 i/o tgr0d input capture input/output compare output/pwm output pin 1 input capture/out compare match a1 tioca1 i/o tgr1a input capture input/output compare output/pwm output pin input capture/out compare match b1 tiocb1 i/o tgr1b input capture input/output compare output/pwm output pin 2 input capture/out compare match a2 tioca2 i/o tgr2a input capture input/output compare output/pwm output pin input capture/out compare match b2 tiocb2 i/o tgr2b input capture input/output compare output/pwm output pin 3 input capture/out compare match a3 tioca3 i/o tgr3a input capture input/output compare output/pwm output pin input capture/out compare match b3 tiocb3 i/o tgr3b input capture input/output compare output/pwm output pin input capture/out compare match c3 tiocc3 i/o tgr3c input capture input/output compare output/pwm output pin input capture/out compare match d3 tiocd3 i/o tgr3d input capture input/output compare output/pwm output pin
356 channel name abbre- viation i/o function 4 input capture/out compare match a4 tioca4 i/o tgr4a input capture input/output compare output/pwm output pin input capture/out compare match b4 tiocb4 i/o tgr4b input capture input/output compare output/pwm output pin 5 input capture/out compare match a5 tioca5 i/o tgr5a input capture input/output compare output/pwm output pin input capture/out compare match b5 tiocb5 i/o tgr5b input capture input/output compare output/pwm output pin 6.6 programmable pulse generator 6.6.1 features ? maximum 16-bit data output capability ? up to four different 4-bit outputs ? output trigger signals can be selected ? non-overlap margin can be set ? can operate together with the data transfer controller (dtc) and dma controller (dmac) ? inverse output can be selected ? module stop mode can be set
357 6.6.2 block diagram compare match signals po15 po14 po13 po12 po11 po10 po9 po8 po7 po6 po5 po4 po3 po2 po1 po0 legend pmr: ppg output mode register pcr: ppg output control register nderh: next data enable register h nderl: next data enable register l ndrh: next data register h ndrl: next data register l podrh: output data register h podrl: output data register l internal data bus pulse output pins, group 3 podrh podrl ndrh ndrl control logic nderh pmr nderl pcr pulse output pins, group 2 pulse output pins, group 1 pulse output pins, group 0 figure 6.6 block diagram of ppg
358 6.6.3 pins table 6.5 ppg pins name abbreviation i/o function pulse output 0 po0 output group 0 pulse output pulse output 1 po1 output pulse output 2 po2 output pulse output 3 po3 output pulse output 4 po4 output group 1 pulse output pulse output 5 po5 output pulse output 6 po6 output pulse output 7 po7 output pulse output 8 po8 output group 2 pulse output pulse output 9 po9 output pulse output 10 po10 output pulse output 11 po11 output pulse output 12 po12 output group 3 pulse output pulse output 13 po13 output pulse output 14 po14 output pulse output 15 po15 output 6.7 8-bit timer 6.7.1 features ? two-channel timer using 8-bit counters as base ? selection of four counter input clocks ? counter clearing can be specified ? timer output by combination of two compare match signals ? cascaded operation possible by connecting both counter channels to form a 16-bit counter ? three interrupt sources for each channel ? a/d converter conversion start trigger can be generated ? module stop mode can be set
359 6.7.2 block diagram external clocks internal clocks /8 /64 /8192 clock 1 compare match a1 clear 1 cmia0 cmib0 ovi0 cmia1 cmib1 ovi1 interrupt signals tmo0 tmri0 internal bus tcora0 comparator a0 comparator b0 tcorb0 tcsr0 tcr0 tcora1 comparator a1 tcnt1 comparator b1 tcorb1 tcsr1 tcr1 tmci0 tmci1 tcnt0 overflow 1 compare match b1 tmo1 tmri1 clock selection control logic clear 0 a/d conversion start request signal overflow 01 compare match b0 clock 0 compare match a0 figure 6.7 block diagram of 8-bit timer
360 6.7.3 pins table 6.6 8-bit timer pins channel name abbreviationi/o function 0 timer output pin 0 tmo0 output compare match output timer clock input pin 0 tmci0 input counter external clock input timer reset input pin 0 tmri0 input counter external reset input 1 timer output pin 1 tmo1 output compare match output timer clock input pin 1 tmci1 input counter external clock input timer reset input pin 1 tmri1 input counter external reset input 6.8 watchdog timer 6.8.1 features ? switchable between watchdog timer mode and interval timer mode ? wdtovf output in watchdog timer mode ? interrupt generation when counter overflows in interval timer mode ? selection of eight counter input clocks
361 6.8.2 block diagram overflow interrupt control wovi (interrupt request signal) wdtovf * internal reset signal reset control rstcsr tcnt tscr /2 /64 /128 /512 /2048 /8192 /32768 /131072 clock clock selection internal clocks bus interface module bus internal bus wdt legend tcsr: timer control/status register tcnt: timer counter rstcsr: reset control/status register note: * the wdtovf figure 6.8 block diagram of wdt 6.8.3 pins table 6.7 wdt pin name abbreviation i/o function watchdog timer overflow wdtovf * output outputs counter overflow signal in watchdog timer mode note: * the wdtovf
362 6.9 serial communication interface 6.9.1 features ? three independent on-chip channels in the h8s/2678 series ? selection of synchronous or asynchronous serial communication mode ? full-duplex communication capability ? selection of lsb-first or msb-first transfer ? built-in baud rate generator allows any bit rate to be selected ? selection of transmit/receive clock source ? dtc and dmac can be activated by four interrupts (eri, rxi, txi, and tei) ? module stop mode can be set 6.9.2 block diagram rxd txd sck clock /4 /16 /64 tei txi rxi eri scmr ssr scr smr transmission/ reception control baud rate generator brr module data bus bus interface internal data bus rdr tsr rsr parity generation tdr legend scmr: smart card mode register rsr: receive shift register rdr: receive data register tsr: transmit shift register tdr: transmit data register smr: serial mode register scr: serial control register ssr: serial status register brr: bit rate register external clock parity check figure 6.9 block diagram of sci
363 6.9.3 pins table 6.8 sci pins channel name abbreviation i/o function 0 serial clock pin 0 sck0 i/o sci0 clock input/output receive data pin 0 rxd0 input sci0 receive data input transmit data pin 0 txd0 output sci0 transmit data output 1 serial clock pin 1 sck1 i/o sci1 clock input/output receive data pin 1 rxd1 input sci1 receive data input transmit data pin 1 txd1 output sci1 transmit data output 2 serial clock pin 2 sck2 i/o sci2 clock input/output receive data pin 2 rxd2 input sci2 receive data input transmit data pin 2 txd2 output sci2 transmit data output
364 6.10 smart card interface 6.10.1 features ? ic card (smart card) interface conforming to iso/iec7816-3 supported as sci extension function ? switching between normal sci and smart card interface by means of register setting ? built-in baud rate generator allows any bit rate to be selected ? dtc and dmac can be activated by three interrupts (txi, rxi, and eri) 6.10.2 block diagram bus interface tdr rsr rdr module data bus tsr scmr ssr scr transmission/ reception control brr baud rate generator internal data bus rxd txd sck parity check parity generation clock /4 /16 /64 txi rxi eri smr legend scmr: smart card mode register rsr: receive shift register rdr: receive data register tsr: transmit shift register tdr: transmit data register smr: serial mode register scr: serial control register ssr: serial status register brr: bit rate register figure 6.10 block diagram of smart card interface
365 6.10.3 pins table 6.9 smart card interface pins channel name abbreviation i/o function 0 serial clock pin 0 sck0 i/o sci0 clock input/output receive data pin 0 rxd0 input sci0 receive data input transmit data pin 0 txd0 output sci0 transmit data output 1 serial clock pin 1 sck1 i/o sci1 clock input/output receive data pin 1 rxd1 input sci1 receive data input transmit data pin 1 txd1 output sci1 transmit data output 2 serial clock pin 2 sck2 i/o sci2 clock input/output receive data pin 2 rxd2 input sci2 receive data input transmit data pin 2 txd2 output sci2 transmit data output 6.11 irda 6.11.1 features ? sci channel 0 txd0 and rxd0 signals can be subjected to waveform encoding/decoding conforming to irda specification version 1.0 (irtxd and irrxd pins) ? infrared transmission/reception conforming to the irda specification version 1.0 system can be implemented by connecting these pins to an infrared transceiver/receiver ? transfer rate can be set by software
366 6.11.2 block diagram pulse encoder pulse decoder ircr txd0/irtxd rxd0/irrxd txd rxd irda sci0 figure 6.11 block diagram of irda 6.11.3 pins table 6.10 irda pins channel name abbreviation i/o function 0 serial clock pin 0 sck0 i/o sci0 clock input/output receive data pin 0 rxd0/irrxd input sci0 receive data input (normal/irda) transmit data pin 0 txd0/irtxd output sci0 transmit data output (normal/irda)
367 6.12 a/d converter 6.12.1 features ? 10-bit resolution ? twelve input channels ? settable analog conversion voltage range ? conversion time: 6.7 ? per channel (at 20 mhz operation) ? selection of single mode or scan mode as operating mode ? four data registers ? sample-and-hold function ? three kinds of conversion start (software, timer conversion start trigger, and adtrg pin) ? a/d conversion end interrupt request generation ? module stop mode can be set
368 6.12.2 block diagram an0 an1 an2 an3 an4 an5 an6 an7 an12 an13 an14 an15 module data bus control circuit internal data bus 10-bit d/a comparator + sample-and-hold circuit bus interface addra successive-approximations register multiplexer av cc v ref av ss legend adcr: a/d control register adcsr: a/d control/status register addra: a/d data register a addrb: a/d data register b addrc: a/d data register c addrd: a/d data register d adtrg figure 6.12 block diagram of a/d converter
369 6.12.3 pins table 6.11 a/d converter pins name abbre- viation i/o function analog power supply pin avcc input analog circuit power supply analog ground pin avss input analog circuit ground and reference voltage reference voltage pin vref input a/d conversion reference voltage analog input pin 0 an0 input channel set 0 (ch3 =1) group 0 analog input analog input pin 1 an1 input analog input pin 2 an2 input analog input pin 3 an3 input analog input pin 4 an4 input channel set 1 (ch3 =1) group 1 analog input analog input pin 5 an5 input analog input pin 6 an6 input analog input pin 7 an7 input analog input pin 12 an12 input channel set 1 (ch3 =0) group 1 analog input analog input pin 13 an13 input analog input pin 14 an14 input analog input pin 15 an15 input a/d external trigger input pin adtrg
370 6.13 d/a converter 6.13.1 features ? 8-bit resolution ? output on two channels to maximum four channels ? maximum conversion time of 10 ? (with 20 pf capacitive load) ? output voltage of 0 v to vref ? d/a output hold function in software standby mode ? module stop mode can be set 6.13.2 block diagram module data bus internal data bus vref avcc da1 (da3) da0 (da2) avss 8-bit d/a control circuit bus interface legend dacr01 (dacr23): d/a control register 01 (d/a control register 23) dadr0 to dadr3: d/a data registers 0 to 3 dadr0 (dadr2) dadr1 (dadr3) dacr01 (dacr23) figure 6.13 block diagram of d/a converter
371 6.13.3 pins table 6.12 d/a converter pins name abbreviation i/o function analog power supply pin avcc input analog circuit power supply analog ground pin avss input analog circuit ground and reference voltage analog output pin 0 da0 output channel 0 analog output analog output pin 1 da1 output channel 1 analog output analog output pin 2 da2 output channel 2 analog output analog output pin 3 da3 output channel 3 analog output reference voltage pin vref input analog circuit reference voltage
372 6.14 ram 6.14.1 features ? sixteen kbytes or eight kbytes of on-chip high-speed static ram ? connected to the cpu by a 16-bit data bus, enabling one-state access to both byte data and word data ? can be enabled or disabled by means of the ram enable bit (rame) in the system control register (syscr) 6.14.2 block diagram internal data bus (upper 8 bits) internal data bus (lower 8 bits) h'ff8000 h'ff8002 h'ff8004 h'ffbffe h'ff8001 h'ff8003 h'ff8005 h'ffbfff figure 6.14 block diagram of ram (16 kbytes)
373 6.15 rom 6.15.1 features ? connected to the bus master by a 16-bit data bus, enabling one-state access to both byte data and word data ? the flash memory version (f-ztat) can be erased and programmed on-board as well as with a prom programmer ? the h8s/2678 has 512 kbytes, the h8s/2676 256 kbytes, and the h8s/2675 128 kbytes, of on- chip mask rom 6.15.2 block diagrams internal data bus (upper 8 bits) internal data bus (lower 8 bits) h'000000 h'000002 h'07fffe h'000001 h'000003 h'07ffff figure 6.15 block diagram of mask rom (256 kbytes)
374 module bus bus interface/controller flash memory (256 kbytes) operating mode internal address bus internal data bus (16 bits) fwe pin mode pins flmcr2 ebr1 ebr2 ramer flmcr1 syscr legend flmcr1: flash memory control register 1 flmcr2: flash memory control register 2 ebr1: erase block register 1 ebr2: erase block register 2 ramer: ram emulation register syscr: system control register figure 6.16 block diagram of flash memory
375 6.16 clock pulse generator 6.16.1 features ? comprises an oscillator, pll (phase-locked loop) circuit, and frequency divider ? generates system clock (? and internal clock 6.16.2 block diagram extal xtal pll circuit ( pin internal clock to on-chip supporting modules sck2 to sck0 sckcr stc0, stc1 pllcr figure 6.17 block diagram of clock pulse generator
376
377 section 7 electrical characteristics 7.1 electrical characteristics of mask rom version (h8s/2677, h8s/2676, h8s/2675, h8s/2673) and romless version (h8s/2670) 7.1.1 absolute maximum ratings table 7.1 lists the absolute maximum ratings. table 7.1 absolute maximum ratings item symbol value unit power supply voltage v cc pllv cc ?.3 to +4.6 v input voltage (except port 4, p54 to p57) v in ?.3 to v cc +0.3 v input voltage (port 4, p54 to p57) v in ?.3 to av cc +0.3 v reference power supply voltage v ref ?.3 to av cc +0.3 v analog power supply voltage av cc ?.3 to +4.6 v analog input voltage v an ?.3 to av cc +0.3 v operating temperature t opr regular specifications: ?0 to +75 ? wide-range specifications: ?0 to +85 ? storage temperature t stg ?5 to +125 ? caution: permanent damage to the chip may result if absolute maximum ratings are exceeded.
378 7.1.2 dc characteristics table 7.2 dc characteristics conditions: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v* 1 , t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) item symbol min typ max unit test conditions schmitt trigger input voltage port 1, port 2, p50 to p53 * 2 , port 6 * 2 , port 8 * 2 , vt v cc 0.2 v pf1 * 2 , pf2 * 2 , ph2 * 2 , ph3 * 2 vt + v cc 0.7 v vt + ?vt av cc 0.07 v p54 to p57 * 2 vt av cc 0.2 v vt + av cc 0.7 v vt + ?vt av cc 0.07 v input high voltage stby , md2 to md0 v ih v cc 0.9 v cc + 0.3 v res , nmi v cc 0.9 v cc + 0.3 v extal v cc 0.7 v cc + 0.3 v port 3, p50 to p53 * 3 , ports 6 to 8 * 3 , ports a to h * 3 v cc 0.7 v cc + 0.3 v port 4, p54 to p57 * 3 av cc 0.7 av cc + 0.3 v input low voltage res , stby , md2 to md0 v il ?.3 v cc 0.1 v nmi, extal ?.3 v cc 0.2 v ports 3 to 8, ports a to h * 3 ?.3 v cc 0.2 v output high all output pins v oh v cc ?0.5 v i oh = ?00 a voltage v cc ?1.0 v i oh = ? ma output low voltage all output pins v ol 0.4 v i ol = 1.6 ma
379 item symbol min typ max unit test conditions input leakage res |i in | 10.0 av in = 0.5 to v cc ?0.5 v current stby , nmi, md2 to md0 1.0 a port 4, p54 to p57 1.0 av in = 0.5 to av cc ?0.5 v three-state leakage current (off state) ports 1 to 3, p50 to p53, ports 6 to 8, ports a to h | i tsi | 1.0 av in = 0.5 to v cc ?0.5 v input pull-up mos current ports a to e i p 10 300 av cc = 2.7 to 3.6 v v in = 0 v input res c in 30 pf v in = 0 v capacitance nmi 30 pf f = 1 mhz all input pins except res and nmi 15 pf t a = 25? current dissipation * 4 normal operation i cc * 6 ?0 (3.3 v) 150 ma f = 33 mhz sleep mode 70 (3.3 v) 125 ma f = 33 mhz standby mode * 5 0.01 10 at a 50? 80 a 50? < t a analog power during a/d and d/a conversion ai cc 0.2 (3.0 v) 2.0 ma supply current idle 0.01 5.0 a reference power during a/d and d/a conversion ai cc 1.4 (3.0 v) 4.0 ma supply current idle 0.01 5.0 a ram standby voltage v ram 2.0 v notes: 1. if the a/d and d/a converters are not used, do not leave the av cc , v ref , and av ss pins open. connect the av cc and v ref pins to v cc , and the av ss pin to v ss . 2. when used as irq0 to irq15 . 3. when used as other than irq0 to irq15 . 4. current dissipation values are for v ih min = v cc ?0.5 v and v il max = 0.5 v with all output pins unloaded and all mos input pull-ups in the off state. 5. the values are for v ram v cc < 2.7 v, v ih min = v cc 0.9, and v il max = 0.3 v.
380 6. i cc depends on v cc and f as follows: i cc max = 1.0 (ma) + tbd (ma/(mhz v)) v cc f (normal operation) i cc max = 1.0 (ma) + tbd (ma/(mhz v)) v cc f (sleep mode) table 7.3 permissible output currents conditions: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v* 1 , t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) item symbol min typ max unit permissible output low current (per pin) all output pins i ol 2.0 ma permissible output low current (total) total of all output pins i ol 80ma permissible output high current (per pin) all output pins ? oh 2.0 ma permissible output high current (total) total of all output pins ? oh 40ma notes: 1. if the a/d and d/a converters are not used, do not leave the av cc , v ref , and av ss pins open. connect the av cc and v ref pins to v cc , and the av ss pin to v ss . 2. to protect chip reliability, do not exceed the output current values in table 7.4.
381 7.1.3 ac characteristics chip output pin crh rl 3 v c = 50 pf: ports a to h c = 30 pf: ports 1 to 3, p50 to p53, ports 6 to 8 cl = 2.4 k ? rh = 12 k ? input/output timing measurement level: 1.5 v (v cc = 2.7 v to 3.6 v) figure 7.1 output load circuit
382 clock timing table 7.4 clock timing condition a*: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 20 mhz, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) condition b: v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 33 mhz, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) * in planning stage condition a condition b test item symbol min max min max unit conditions clock cycle time t cyc 50 500 30.3 500 ns figure 7.2 clock pulse high width t ch 20 10 ns figure 7.2 clock pulse low width t cl 20 10 ns clock rise time t cr ? ? ns clock fall time t cf ? ? ns reset oscillation stabilization time (crystal) t osc1 10 10 ms figure 7.3(1) software standby oscillation stabilization time (crystal) t osc2 10 10 ms figure 7.3(2) external clock output delay stabilization time t dext 500 500 s figure 7.3(1)
383 t cyc t ch t cf t cl t cr figure 7.2 system clock timing extal v cc stby res t dext t osc1 t dext t osc1 figure 7.3 (1) oscillation stabilization timing
384 oscillator software standby mode (power-down mode) oscillation stabilization time t osc2 nmi nmi exception handling nmieg = 1 ssby = 1 nmi exception handling sleep instruction nmieg ssby figure 7.3 (2) oscillation stabilization timing
385 control signal timing table 7.5 control signal timing condition a*: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 20 mhz, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) condition b: v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 33 mhz, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) * in planning stage condition a condition b test item symbol min max min max unit conditions res setup time t ress 200 200 ns figure 7.4 res pulse width t resw 20 20 t cyc nmi setup time t nmis 150 150 ns figure 7.5 nmi hold time t nmih 10 10 nmi pulse width (in recovery from software standby mode) t nmiw 200 200 irq setup time t irqs 150 150 ns irq hold time t irqh 10 10 irq pulse width (in recovery from software standby mode) t irqw 200 200
386 res t ress t ress t resw figure 7.4 reset input timing nmi irqi (i = 0 to 15) * irq (edge input) irq note: * necessary for ssier setting to clear software standby mode. t nmis t nmih t irqs t irqs t irqh t nmiw t irqw figure 7.5 interrupt input timing
387 bus timing table 7.6 bus timing condition a*: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, = 2 mhz to 20 mhz, t a = 20 c to +75 c (regular specifications), t a = 40 c to +85 c (wide-range specifications) condition b: v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, = 2 mhz to 33 mhz, t a = 20 c to +75 c (regular specifications), t a = 40 c to +85 c (wide-range specifications) * in planning stage condition a condition b test item symbol min max min max unit conditions address delay time t ad 20 20 ns figure 7.6 to figure 7.19 address setup time 1 t as1 0.5 t cyc 15 0.5 t cyc 13 ns address setup time 2 t as2 1.0 t cyc 15 1.0 t cyc 13 ns address setup time 3 t as3 1.5 t cyc 15 1.5 t cyc 13 ns address setup time 4 t as4 2.0 t cyc 15 2.0 t cyc 13 ns address hold time 1 t ah1 0.5 t cyc 10 0.5 t cyc 8 ns address hold time 2 t ah2 1.0 t cyc 10 1.0 t cyc 8 ns address hold time 3 t ah3 1.5 t cyc 10 1.5 t cyc 8 ns cs delay time 1 t csd1 20 15 ns cs delay time 2 t csd2 20 15 ns cs delay time 3 t csd3 20 20 ns as delay time t asd 20 15 ns rd delay time 1 t rsd1 20 15 ns rd delay time 2 t rsd2 20 15 ns read data setup time 1 t rds1 15 15 ns read data setup time 2 t rds2 15 15 ns read data hold time 1 t rdh1 0 0 ns
388 condition a condition b test item symbol min max min max unit conditions read data hold time 2 t rdh2 0 0 ns figure 7.6 to figure 7.19 read data access time 1 t ac1 1.0 t cyc 25 1.0 t cyc 20 ns read data access time 2 t ac2 1.5 t cyc 25 1.5 t cyc 20 ns read data access time 3 t ac3 2.0 t cyc 25 2.0 t cyc 20 ns read data access time 4 t ac4 2.5 t cyc 25 2.5 t cyc 20 ns read data access time 5 t ac5 1.0 t cyc 25 1.0 t cyc 20 ns read data access time 6 t ac6 2.0 t cyc 25 2.0 t cyc 20 ns read data access time 7 t ac7 4.0 t cyc 25 4.0 t cyc 20 ns read data access time 8 t ac8 3.0 t cyc 25 3.0 t cyc 20 ns address read data access time 1 t aa1 1.0 t cyc 25 1.0 t cyc 20 ns address read data access time 2 t aa2 1.5 t cyc 25 1.5 t cyc 20 ns address read data access time 3 t aa3 2.0 t cyc 25 2.0 t cyc 20 ns address read data access time 4 t aa4 2.5 t cyc 25 2.5 t cyc 20 ns address read data access time 5 t aa5 3.0 t cyc 25 3.0 t cyc 20 ns wr delay time 1 t wrd1 20 15 ns wr delay time 2 t wrd2 20 15 ns wr pulse width 1 t wsw1 1.0 t cyc 20 1.0 t cyc 13 ns wr pulse width 2 t wsw2 1.5 t cyc 20 1.5 t cyc 13 ns write data delay time t wdd 30 20 ns write data setup time 1 t wds1 0.5 t cyc 20 0.5 t cyc 13 ns
389 condition a condition b test item symbol min max min max unit conditions write data setup time 2 t wds2 1.0 t cyc 20 1.0 t cyc 13 ns figure 7.6 to figure 7.19 write data setup time 3 t wds3 1.5 t cyc 20 1.5 t cyc 13 ns write data hold time 1 t wdh1 0.5 t cyc 10 0.5 t cyc 8 ns write data hold time 2 t wdh2 1.0 t cyc 10 1.0 t cyc 8 ns write data hold time 3 t wdh3 1.5 t cyc 10 1.5 t cyc 8 ns write command setup time 1 t wcs1 0.5 t cyc 10 0.5 t cyc 10 ns write command setup time 2 t wcs2 1.0 t cyc 10 1.0 t cyc 10 ns write command hold time 1 t wch1 0.5 t cyc 10 0.5 t cyc 10 ns write command hold time 2 t wch2 1.0 t cyc 10 1.0 t cyc 10 ns read command setup time 1 t rcs1 1.5 t cyc 10 1.5 t cyc 10 ns read command setup time 2 t rcs2 2.0 t cyc 10 2.0 t cyc 10 ns read command hold time t rch 0.5 t cyc 10 0.5 t cyc 10 ns cas delay time 1 t casd1 20 15 ns cas delay time 2 t casd2 20 15 ns cas setup time 1 t csr1 0.5 t cyc 10 0.5 t cyc 10 ns cas setup time 2 t csr2 1.5 t cyc 10 1.5 t cyc 10 ns cas pulse width 1 t casw1 1.0 t cyc 20 1.0 t cyc 20 ns cas pulse width 2 t casw2 1.5 t cyc 20 1.5 t cyc 20 ns cas precharge time 1 t cpw1 1.0 t cyc 20 1.0 t cyc 20 ns cas precharge time 2 t cpw2 1.5 t cyc 20 1.5 t cyc 20 ns oe delay time 1 t oed1 20 15 ns oe delay time 2 t oed2 20 15 ns
390 condition a condition b test item symbol min max min max unit conditions precharge time 1 t pch1 1.0 t cyc 20 1.0 t cyc 20 ns figure 7.6 to figure 7.19 precharge time 2 t pch2 1.5 t cyc 20 1.5 t cyc 20 ns self-refresh precharge time 1 t rps1 2.5 t cyc 20 2.5 t cyc 20 ns figure 7.20 figure 7.21 self-refresh precharge time 2 t rps2 3.0 t cyc 20 3.0 t cyc 20 ns wait setup time t wts 30 25 ns figure 7.14 wait hold time t wth 5 5 ns breq setup time t breqs 30 30 ns figure 7.22 back delay time t bacd 15 15 ns bus floating time t bzd 50 40 ns breqo delay time t brqod 30 25 ns figure 7.23
391 t1 t2 a23 to a0 cs7 to cs0 as rd d15 to d0 rd d15 to d0 hwr , lwr d15 to d0 read (rdnn = 1) read (rdnn = 0) write t ad t csd1 t as1 t as1 t as1 t as1 t rsd1 t rsd1 t ac5 t aa2 t rsd1 t wrd2 t wsw1 t wdh1 t wdd t wrd2 t ah1 t ac2 t rds2 t aa3 t rsd2 t rds1 t rdh1 t ah1 t asd t asd dack0 , dack1 edack0 to edack3 t dacd1 t dacd2 t edacd1 t edacd2 t rdh2 figure 7.6 basic bus timing: two-state access
392 t1 a23 to a0 cs7 to cs0 as rd d15 to d0 rd d15 to d0 hwr , lwr d15 to d0 t2 t3 read (rdnn = 1) read (rdnn = 0) write t ad t as1 t ah1 t rsd1 t rds1 t rdh1 t rsd2 t rds2 t rdh2 t asd t asd t rsd1 t rsd1 t ac6 t ac4 t aa5 t as2 t wsw2 t wds1 t wrd1 t wrd2 t ah1 t aa4 t as1 t as1 t csd1 dack0 , dack1 edack0 to edack3 t dacd1 t dacd2 t edacd1 t edacd2 t wdh1 t wdd figure 7.7 basic bus timing: three-state access
393 t1 a23 to a0 cs7 to cs0 as rd d15 to d0 rd d15 to d0 hwr , lwr d15 to d0 wait t wts t wth t wts t wth t2 tw t3 read (rdnn = 1) read (rdnn = 0) write figure 7.8 basic bus timing: three-state access, one wait
394 th t ad t csd1 t as1 t asd t as3 t rsd1 t ac5 t rds1 t rdh1 t ah2 t ah3 t wdh3 t wsw1 t wds2 t wdd t as3 t wrd2 t wrd2 t rsd2 t rsd1 t ac2 t rds2 t rdh2 t as3 t rsd1 t ah3 t ah1 t asd a23 to a0 cs7 to cs0 as rd d15 to d0 rd d15 to d0 hwr , lwr d15 to d0 t1 t2 tt read (rdnn = 1) read (rdnn = 0) write dack0 , dack1 edack0 to edack3 t dacd1 t dacd2 t edacd1 t edacd2 figure 7.9 basic bus timing: two-state access ( cs assertion period extended)
395 th t ad t csd1 t as1 t asd t as3 t rsd1 t rsd1 t asd t ah1 t ah3 t ah2 t ah3 t wdh3 t wsw2 t wds3 t as4 t as3 t rsd1 t wrd2 t wrd1 t ac4 t rdh2 t rsd2 t ac6 t rdh1 t1 t2 t3 tt a23 to a0 cs7 to cs0 as rd d15 to d0 rd d15 to d0 d15 to d0 hwr , lwr read (rdnn = 1) read (rdnn = 0) write dack0 , dack1 edack0 to edack3 t dacd1 t dacd2 t edacd1 t edacd2 t rds2 t wdd t rds1 figure 7.10 basic bus timing: three-state access ( cs assertion period extended)
396 t1 a23 to a6, a0 a5 to a1 cs7 to cs0 as rd d15 to d0 hwr , lwr t2 t1 t ad t rsd2 t aa1 t rds2 t rdh2 t1 read figure 7.11 burst rom access timing: one-state burst access
397 t1 a23 to a6, a0 a5 to a1 cs7 to cs0 as rd d15 to d0 hwr , lwr t2 t3 t1 t ad t as1 t asd t aa3 t rsd2 t rds2 t rdh2 t asd t ah1 t2 read figure 7.12 burst rom access timing: two-state burst access
398 tp t ad t as3 t ah1 t csd2 t pch2 t as2 t ac1 t oed1 t oed1 t aa3 t ac4 t wcs1 t wch1 t wrd2 t wdd t wds1 t wdh2 t rds2 t rdh2 t ah2 t csd3 t casd1 t casd1 t casw1 t ad a23 to a0 ras5 to ras2 ucas lcas oe , rd hwr d15 to d0 oe , rd hwr d15 to d0 as tr tc1 tc2 read write dack0 , dack1 edack0 to edack3 t dacd1 t dacd2 t edacd1 t edacd2 note: dack and edack timing: when dds = 0 and edds = 0 ras timing: when rast = 0 t wrd2 figure 7.13 dram access timing: two-state access
399 tp tr tc1 tcw tcwp tc2 a23 to a0 ras5 to ras2 ucas , lcas oe , rd hwr d15 to d0 ucas , lcas oe , rd hwr t wts t wth t wts t wth d15 to d0 as wait read write tcw: wait cycle inserted by programmable wait function tcwp: wait cycle inserted by pin wait function dack0 , dack1 edack0 to edack3 dack and edack timing: when dds = 0 and edds = 0 ras timing: when rast = 0 note: figure 7.14 dram access timing: two-state access, one wait
400 tp a23 to a0 ras5 to ras2 ucas lcas oe , rd hwr d15 to d0 oe , rd hwr d15 to d0 as tr tc1 t cpw1 t ac3 t rch t rcs1 tc2 tc1 tc2 read write dack and edack timing: when dds = 1 and edds = 1 ras timing: when rast = 0 note: dack0 , dack1 edack0 to edack3 t dacd1 t dacd2 t edacd1 t edacd2 figure 7.15 dram access timing: two-state burst access
401 tp t ad t ad t as2 t ah2 t csd2 t pch1 t as3 t csd3 t casd1 t ah3 t casd2 t casw2 t ac2 t aa5 t ac7 t wrd2 t wdd t wds2 t wdh3 t wcs2 t wch2 t rdh2 t oed2 t oed1 a23 to a0 ras5 to ras2 ucas lcas oe , rd hwr d15 to d0 oe , rd hwr d15 to d0 as tr tc1 tc2 tc3 write read dack and edack timing: when dds = 0 and edds = 0 ras timing: when rast = 1 note: dack0 , dack1 edack0 to edack3 t dacd1 t dacd2 t edacd1 t edacd2 t wrd2 t rds2 figure 7.16 dram access timing: three-state access (rast = 1)
402 tp tr tc1 tc2 tc3 tc1 tc2 tc3 a23 to a0 ras5 to ras0 ucas lcas oe , rd hwr d15 to d0 oe , rd hwr t rch t rcs2 t ac8 t cpw2 d15 to d0 as read write dack and edack timing: when dds = 1 and edds = 1 ras timing: when rast = 1 note: dack0 , dack1 edack0 to edack3 figure 7.17 dram access timing: three-state burst access
403 trp ras5 to ras2 ucas , lcas oe trr t csd2 t csr1 t casd1 t casd1 t csd1 trc1 trc2 figure 7.18 cas-before-ras refresh timing trp ras5 to ras2 ucas , lcas oe trrw t csd2 t csr2 t casd1 t csd1 t casd1 trr trc1 trcw trc2 figure 7.19 cas-before-ras refresh timing (with wait cycle insertion)
404 trp ras5 to ras2 ucas , lcas oe trr t csd2 t casd1 t csd2 t casd1 t rps2 trc trc tpsr tp tr dram access self-refresh figure 7.20 self-refresh timing (return from software standby mode: rast = 0) trp ras5 to ras2 ucas to lcas oe trr t csd2 t casd1 t csd2 t casd1 t rps1 trc trc tpsr tp tr dram access self-refresh figure 7.21 self-refresh timing (return from software standby mode: rast = 1)
405 breq t breqs t breqs t bacd t bzd t bacd t bzd back a23 to a0 cs7 to cs0 (ras5 to ras2) d15 to d0 as , rd hwr , lwr ucas , lcas , oe figure 7.22 external bus release timing back t brqod t brqod breqo figure 7.23 external bus request output timing
406 dmac and exdmac timing table 7.7 dmac and exdmac timing condition a*: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, = 2 mhz to 20 mhz, t a = 20 c to +75 c (regular specifications), t a = 40 c to +85 c (wide-range specifications) condition b: v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, = 2 mhz to 33 mhz, t a = 20 c to +75 c (regular specifications), t a = 40 c to +85 c (wide-range specifications) * in planning stage condition a condition b test item symbol min max min max unit conditions dreq setup time t drqs 30 25 ns figure7.27 dreq hold time t drqh 10 10 tend delay time t ted 20 18 ns figure7.26 dack delay time 1 t dacd1 20 18 figure7.24 dack delay time 2 t dacd2 20 18 figure7.25 edreq setup time t edrqs 30 25 ns figure7.27 edreq hold time t edrqh 10 10 etend delay time t eted 20 18 ns figure7.26 edack delay time 1 t edacd1 20 18 figure7.24 edack delay time 2 t edacd2 20 18 figure7.25 edrak delay time t edrkd 20 18 ns figure7.28
407 t1 a23 to a0 cs7 to cs0 as t dacd1 t dacd2 t edacd1 t edacd2 rd (read) d15 to d0 (read) hwr , lwr (write) d15 to d0 (write) dack0 , dack1 edack0 to edack3 t2 figure 7.24 dmac and exdmac single address transfer timing: two-state access
408 t1 t dacd1 t edacd1 t dacd2 t edacd2 a 23 to a0 c s7 to cs0 a s r d ( read) d 15 to d0 ( read) h wr , lwr ( write) d 15 to d0 ( write) d ack0 , dack1 e dack0 to edack3 t2 t3 figure 7.25 dmac and exdmac single address transfer timing: three-state access
409 t1 t ted t eted t ted t eted tend0 , tend1 etend0 to etend3 t2 or t3 figure 7.26 dmac and exdmac tend / etend output timing dreq0 , dreq1 t drqs t edrqs t drqh t derqh edreq0 to edreq3 figure 7.27 dmac and exdmac dreq / edreq input timing edrak0 to edrak3 t edrkd t edrkd figure 7.28 exdmac edrak output timing
410 timing of on-chip supporting modules table 7.8 timing of on-chip supporting modules condition a*: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, = 2 mhz to 20 mhz, t a = 20 c to +75 c (regular specifications), t a = 40 c to +85 c (wide-range specifications) condition b: v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, = 2 mhz to 33 mhz, t a = 20 c to +75 c (regular specifications), t a = 40 c to +85 c (wide-range specifications) * in planning stage condition a condition b test item symbol min max min max unit conditions i/o ports output data delay time t pwd 50 40 ns figure7.29 input data setup time t prs 30 25 ns input data hold time t prh 30 25 ns ppg pulse output delay time t pod 50 40 ns figure7.30 tpu timer output delay time t tocd 50 40 ns figure7.31 timer input setup time t tics 30 25 ns timer clock input setup time t tcks 30 25 ns figure7.32 timer clock single-edge specification t tckwh 1.5 1.5 t cyc pulse width both-edge specification t tckwl 2.5 2.5 t cyc
411 condition a condition b test item symbol min max min max unit conditions 8-bit timer timer output delay time t tmod 50 40 ns figure7.33 timer reset input setup time t tmrs 30 25 ns figure7.35 timer clock input setup time t tmcs 30 25 ns figure7.34 timer clock single-edge specification t tmcwh 1.5 1.5 t cyc pulse width both-edge specification t tmcwl 2.5 2.5 t cyc wdt overflow output delay time t wovd 50 40 ns figure7.36 sci input clock asynchronous t scyc 4 4 t cyc figure7.37 cycle synchronous 6 6 input clock pulse width t sckw 0.4 0.6 0.4 0.6 t scyc input clock rise time t sckr 1.5 1.5 t cyc input clock fall time t sckf 1.5 1.5 transmit data delay time t txd 50 40 ns figure7.38 receive data setup time (synchronous) t rxs 50 40 ns receive data hold time (synchronous) t rxh 50 40 ns a/d converter trigger input setup time t trgs 30 30 ns figure7.39
412 t1 t prs t prh t pwd t2 ports 1 to 8, a to h (read) ports 1 to 3, 6 to 9, p53 to p50, ports a to h (write) figure 7.29 i/o port input/output timing po15 to po0 t pod figure 7.30 ppg output timing output compare output * input capture input * t tocd t tics note: * tioca0 to tioca5, tiocb0 to tiocb5, tiocc0, tiocc3, tiocd0, tiocd3 figure 7.31 tpu input/output timing
413 tclka to tclkd t tckwl t tckwh t tcks t tcks figure 7.32 tpu clock input timing tmo0, tmo1 t tmod figure 7.33 8-bit timer output timing tmci0, tmci1 t tmcwl t tmcwh t tmcs t tmcs figure 7.34 8-bit timer clock input timing tmri0, tmri1 t tmrs figure 7.35 8-bit timer reset input timing
414 wdtovf t wovd t wovd figure 7.36 wdt output timing sck0 to sck2 t sckw t sckr t sckf t scyc figure 7.37 sck clock input timing sck0 to sck2 t txd t rxs t rxh txd0 to txd2 (transmit data) rxd0 to rxd2 (receive data) figure 7.38 sci input/output timing: synchronous mode adtrg t trgs figure 7.39 a/d converter external trigger input timing
415 7.1.4 a/d conversion characteristics table 7.9 a/d conversion characteristics condition a*: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, = 2 mhz to 20 mhz, t a = 20 c to +75 c (regular specifications), t a = 40 c to +85 c (wide-range specifications) condition b: v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, = 2 mhz to 33 mhz, t a = 20 c to +75 c (regular specifications), t a = 40 c to +85 c (wide-range specifications) * in planning stage condition a condition b item min typ max min typ max unit resolution 10 10 10 10 10 10 bit conversion time 6.7 8.1 s analog input capacitance 20 20 pf permissible signal source impedance 5 5k ? nonlinearity error 7.5 7.5 lsb offset error 7.5 7.5 lsb full-scale error 7.5 7.5 lsb quantization error 0.5 0.5 lsb absolute accuracy 8.0 8.0 lsb
416 7.1.5 d/a conversion characteristics table 7.10 d/a conversion characteristics condition a*: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, = 2 mhz to 20 mhz, t a = 20 c to +75 c (regular specifications), t a = 40 c to +85 c (wide-range specifications) condition b: v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, = 2 mhz to 33 mhz, t a = 20 c to +75 c (regular specifications), t a = 40 c to +85 c (wide-range specifications) * in planning stage condition a condition b item min typ max min typ max unit test conditions resolution 8 8 8 8 8 8 bit conversion time 10 10 s 20 pf capacitive load absolute accuracy 2.0 3.0 2.0 3.0 lsb 2 m ? resistive load 2.0 2.0 lsb 4 m ? resistive load
417 7.2 electrical characteristics of f-ztat version (h8s/2677, h8s/2676) 7.2.1 absolute maximum ratings table 7.11 lists the absolute maximum ratings. table 7.11 absolute maximum ratings item symbol value unit power supply voltage v cc pllv cc 0.3 to +4.0 v input voltage (fwe) v in 0.3 to v cc +0.3 v input voltage (except port 4, p54 to p57) v in 0.3 to v cc +0.3 v input voltage (port 4, p54 to p57) v in 0.3 to av cc +0.3 v reference power supply voltage v ref 0.3 to av cc +0.3 v analog power supply voltage av cc 0.3 to +4.0 v analog input voltage v an 0.3 to av cc +0.3 v operating temperature t opr regular specifications: 20 to +75 * c wide-range specifications: 40 to +85 * c storage temperature t stg 55to +125 c caution: permanent damage to the chip may result if absolute maximum ratings are exceeded. note: * the operating temperature ranges for flash memory programming/erasing are as follows: t a = 0 c to +75 c (regular specifications) t a = 0 c to +85 c (wide-range specifications)
418 7.2.2 dc characteristics table 7.12 dc characteristics conditions: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v* 1 , t a = 20 c to +75 c (regular specifications), t a = 40 c to +85 c (wide-range specifications) item symbol min typ max unit test conditions schmitt trigger input voltage port 1, port 2, p50 to p53 * 2 , port 6 * 2 , port 8 * 2 , vt v cc 0.2 v pf1 * 2 , pf2 * 2 , ph2 * 2 , ph3 * 3 vt + v cc 0.7 v vt + vt v cc 0.07 v p54 to p57 * 2 vt av cc 0.2 v vt + av cc 0.7 v vt + vt v cc 0.07 v input high voltage stby , md2 to md0 v ih v cc 0.9 v cc + 0.3 v res , nmi, fwe v cc 0.9 v cc + 0.3 v extal v cc 0.7 v cc + 0.3 v port 3, p50 to p53 * 3 , ports 6 to 8 * 3 , ports a to h * 3 v cc 0.7 v cc + 0.3 v port 4, p54 to p57 * 3 av cc 0.7 av cc + 0.3 v input low voltage res , stby , md2 to md0, fwe v il 0.3 v cc 0.1 v nmi, extal 0.3 v cc 0.2 v ports 3 to 8, ports a to h * 3 0.3 v cc 0.2 v output high all output pins v oh v cc 0.5 vi oh = 200 a voltage v cc 1.0 vi oh = 1 ma output low voltage all output pins v ol 0.4 v i ol = 1.6 ma
419 item symbol min typ max unit test conditions input leakage res |i in | 10.0 av in = 0.5 to v cc 0.5 v current stby , nmi, md2 to md0 1.0 a port 4, p54 to p57 1.0 av in = 0.5 to av cc 0.5 v three-state leakage current (off state) ports 1 to 3, p50 to p53, ports 6 to 8, ports a to h |i tsi | 1.0 av in = 0.5 to v cc 0.5 v input pull-up mos current ports a to e i p 10 300 av cc = 2.7 to 3.6 v v in = 0 v input res c in 30 pf v in = 0 v capacitance nmi 30 pf f = 1 mhz all input pins except res and nmi 15 pf t a = 25 c current dissipation * 4 normal operation i cc * 6 80 (3.3 v) 150 ma f = 33 mhz sleep mode 70 (3.3 v) 125 ma f = 33 mhz standby mode * 5 0.01 10 at a 50 c 80 a50 c < t a analog power during a/d and d/a conversion ai cc 0.3 (3.0 v) 2.0 ma supply current idle 0.01 5.0 a reference power during a/d and d/a conversion ai cc 1.4 (3.0 v) 4.0 ma supply current idle 0.01 5.0 a ram standby voltage v ram 2.0 v notes: 1. if the a/d and d/a converters are not used, do not leave the av cc , v ref , and av ss pins open. connect the av cc and v ref pins to v cc , and the av ss pin to v ss . 2. when used as irq0 to irq15 . 3. when used as other than irq0 to irq15 . 4. current dissipation values are for v ih min = v cc 0.5 v and v il max = 0.5 v with all output pins unloaded and all mos input pull-ups in the off state. 5. the values are for v ram v cc < 2.7 v, v ih min = v cc 0.9, and v il max = 0.3 v.
420 6. i cc depends on v cc and f as follows: i cc max = 1.0 (ma) + tbd (ma/(mhz v)) v cc f (normal operation) i cc max = 1.0 (ma) + tbd (ma/(mhz v)) v cc f (sleep mode) table 7.13 permissible output currents conditions: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v* 1 , t a = 20 c to +75 c (regular specifications), t a = 40 c to +85 c (wide-range specifications) item symbol min typ max unit permissible output low current (per pin) all output pins i ol 2.0 ma permissible output low current (total) total of all output pins i ol 80 ma permissible output high current (per pin) all output pins i oh 2.0 ma permissible output high current (total) total of all output pins i oh 40 ma notes: 1. if the a/d and d/a converters are not used, do not leave the av cc , v ref , and av ss pins open. connect the av cc and v ref pins to v cc , and the av ss pin to v ss . 2. to protect chip reliability, do not exceed the output current values in table 7.16.
421 7.2.3 ac characteristics clock timing table 7.14 clock timing condition a*: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, = 2 mhz to 20 mhz, t a = 20 c to +75 c (regular specifications), t a = 40 c to +85 c (wide-range specifications) condition b: v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, = 2 mhz to 33 mhz, t a = 20 c to +75 c (regular specifications), t a = 40 c to +85 c (wide-range specifications) note: * in planning stage condition a condition b test item symbol min max min max unit conditions clock cycle time t cyc 50 500 30.3 500 ns figure7.2 clock pulse high width t ch 20 10 ns figure7.2 clock pulse low width t cl 20 10 ns clock rise time t cr 5 5ns clock fall time t cf 5 5ns reset oscillation settling time (crystal) t osc1 10 10 ms figure7.3 software standby oscillation settling time (crystal) t osc2 10 10 ms external clock output delay settling time t dext 500 500 s figure7.3
422 control signal timing table 7.15 control signal timing condition a*: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v re f = 2.7 v to av cc , v ss = av ss = 0 v, = 2 mhz to 20 mhz, t a = 20 c to +75 c (regular specifications), t a = 40 c to +85 c (wide-range specifications) condition b: v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, = 2 mhz to 33 mhz, t a = 20 c to +75 c (regular specifications), t a = 40 c to +85 c (wide-range specifications) * in planning stage condition a condition b test item symbol min max min max unit conditions res setup time t ress 200 200 ns figure7.4 res pulse width t resw 20 20 t cyc nmi setup time t nmis 150 150 ns figure7.5 nmi hold time t nmih 10 10 nmi pulse width (in recovery from software standby mode) t nmiw 200 200 irq setup time t irqs 150 150 ns irq hold time t irqh 10 10 irq pulse width (in recovery from software standby mode) t irqw 200 200
423 bus timing table 7.16 bus timing condition a*: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, = 2 mhz to 20 mhz, t a = 20 c to +75 c (regular specifications), t a = 40 c to +85 c (wide-range specifications) condition b: v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, = 2 mhz to 33 mhz, t a = 20 c to +75 c (regular specifications), t a = 40 c to +85 c (wide-range specifications) * in planning stage condition a condition b test item symbol min max min max unit conditions address delay time t ad 20 20 ns figure7.6 to figure7.19 address setup time 1 t as1 0.5 t cyc 15 0.5 t cyc 13 ns address setup time 2 t as2 1.0 t cyc 15 1.0 t cyc 13 ns address setup time 3 t as3 1.5 t cyc 15 1.5 t cyc 13 ns address setup time 4 t as4 2.0 t cyc 15 2.0 t cyc 13 ns address hold time 1 t ah1 0.5 t cyc 10 0.5 t cyc 8 ns address hold time 2 t ah2 1.0 t cyc 10 1.0 t cyc 8 ns address hold time 3 t ah3 1.5 t cyc 10 1.5 t cyc 8 ns cs delay time 1 t csd1 20 15 ns cs delay time 2 t csd2 20 15 ns cs delay time 3 t csd3 20 20 ns as delay time t asd 20 15 ns rd delay time 1 t rsd1 20 15 ns rd delay time 2 t rsd2 20 15 ns read data setup time 1 t rds1 15 15 ns read data setup time 2 t rds2 15 15 ns
424 condition a condition b test item symbol min max min max unit conditions read data hold time 1 t rdh1 0 0 ns figure7.6 to figure7.19 read data hold time 2 t rdh2 0 0 ns read data access time 1 t ac1 1.0 t cyc 25 1.0 t cyc 20 ns read data access time 2 t ac2 1.5 t cyc 25 1.5 t cyc 20 ns read data access time 3 t ac3 2.0 t cyc 25 2.0 t cyc 20 ns read data access time 4 t ac4 2.5 t cyc 25 2.5 t cyc 20 ns read data access time 5 t ac5 1.0 t cyc 25 1.0 t cyc 20 ns read data access time 6 t ac6 2.0 t cyc 25 2.0 t cyc 20 ns read data access time 7 t ac7 4.0 t cyc 25 4.0 t cyc 20 ns read data access time 8 t ac8 3.0 t cyc 25 3.0 t cyc 20 ns address read data access time 1 t aa1 1.0 t cyc 25 1.0 t cyc 20 ns address read data access time 2 t aa2 1.5 t cyc 25 1.5 t cyc 20 ns address read data access time 3 t aa3 2.0 t cyc 25 2.0 t cyc 20 ns address read data access time 4 t aa4 2.5 t cyc 25 2.5 t cyc 20 ns address read data access time 5 t aa5 3.0 t cyc 25 3.0 t cyc 20 ns wr delay time 1 t wrd1 20 15 ns wr delay time 2 t wrd2 20 15 ns wr pulse width 1 t wsw1 1.0 t cyc 20 1.0 t cyc 13 ns wr pulse width 2 t wsw2 1.5 t cyc 20 1.5 t cyc 13 ns
425 condition a condition b test item symbol min max min max unit conditions write data delay time t wdd 30 20 ns figure7.6 to figure7.19 write data setup time 1 t wds1 0.5 t cyc 20 0.5 t cyc 13 ns write data setup time 2 t wds2 1.0 t cyc 20 1.0 t cyc 13 ns write data setup time 3 t wds3 1.5 t cyc 20 1.5 t cyc 13 ns write data hold time 1 t wdh1 0.5 t cyc 10 0.5 t cyc 8 ns write data hold time 2 t wdh2 1.0 t cyc 10 1.0 t cyc 8 ns write data hold time 3 t wdh3 1.5 t cyc 10 1.5 t cyc 8 ns write command setup time 1 t wcs1 0.5 t cyc 10 0.5 t cyc 10 ns write command setup time 2 t wcs2 1.0 t cyc 10 1.0 t cyc 10 ns write command hold time 1 t wch1 0.5 t cyc 10 0.5 t cyc 10 ns write command hold time 2 t wch2 1.0 t cyc 10 1.0 t cyc 10 ns read command setup time 1 t rcs1 1.5 t cyc 10 1.5 t cyc 10 ns read command setup time 2 t rcs2 2.0 t cyc 10 2.0 t cyc 10 ns read command hold time t rch 0.5 t cyc 10 0.5 t cyc 10 ns cas delay time 1 t casd1 20 15 ns cas delay time 2 t casd2 20 15 ns cas setup time 1 t csr1 0.5 t cyc 10 0.5 t cyc 10 ns cas setup time 2 t csr2 1.5 t cyc 10 1.5 t cyc 10 ns cas pulse width 1 t casw1 1.0 t cyc 20 1.0 t cyc 20 ns cas pulse width 2 t casw2 1.5 t cyc 20 1.5 t cyc 20 ns
426 condition a condition b test item symbol min max min max unit conditions cas precharge time 1 t cpw1 1.0 t cyc 20 1.0 t cyc 20 ns figure7.6 to figure7.19 cas precharge time 2 t cpw2 1.5 t cyc 20 1.5 t cyc 20 ns oe delay time 1 t oed1 20 15 ns oe delay time 2 t oed2 20 15 ns precharge time 1 t pch1 1.0 t cyc 20 1.0 t cyc 20 ns precharge time 2 t pch2 1.5 t cyc 20 1.5 t cyc 20 ns self-refresh precharge time 1 t rps1 2.5 t cyc 20 2.5 t cyc 20 ns figure7.20 figure7.21 self-refresh precharge time 2 t rps2 3.0 t cyc 20 3.0 t cyc 20 ns wait setup time t wts 30 25 ns figure7.14 wait hold time t wth 5 5 ns breq setup time t breqs 30 30 ns figure7.22 back delay time t bacd 15 15 ns bus floating time t bzd 50 40 ns breqo delay time t brqod 30 25 ns figure7.23
427 dmac and exdmac timing table 7.17 dmac and exdmac timing condition a*: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, = 2 mhz to 20 mhz, t a = 20 c to +75 c (regular specifications), t a = 40 c to +85 c (wide-range specifications) condition b: v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, = 2 mhz to 33 mhz, t a = 20 c to +75 c (regular specifications), t a = 40 c to +85 c (wide-range specifications) * in planning stage condition a condition b test item symbol min max min max unit conditions dreq setup time t drqs 30 25 ns figure7.27 dreq hold time t drqh 10 10 tend delay time t ted 20 18 ns figure7.26 dack delay time 1 t dacd1 20 18 figure7.24 dack delay time 2 t dacd2 20 18 figure7.25 edreq setup time t edrqs 30 25 ns figure7.27 edreq hold time t edrqh 10 10 etend delay time t eted 20 18 ns figure7.26 edack delay time 1 t edacd1 20 18 figure7.24 edack delay time 2 t edacd2 20 18 figure7.25 edrak delay time t edrkd 20 18 ns figure7.28
428 timing of on-chip supporting modules table 7.18 timing of on-chip supporting modules condition a*: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, = 2 mhz to 20 mhz, t a = 20 c to +75 c (regular specifications), t a = 40 c to +85 c (wide-range specifications) condition b: v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, = 2 mhz to 33 mhz, t a = 20 c to +75 c (regular specifications), t a = 40 c to +85 c (wide-range specifications) * in planning stage condition a condition b test item symbol min max min max unit conditions i/o ports output data delay time t pwd 50 40 ns figure 7.29 input data setup time t prs 30 25 ns input data hold time t prh 30 25 ns ppg pulse output delay time t pod 50 40 ns figure 7.30 tpu timer output delay time t tocd 50 40 ns figure 7.31 timer input setup time t tics 30 25 ns timer clock input setup time t tcks 30 25 ns figure 7.32 timer clock single-edge specification t tckwh 1.5 1.5 t cyc pulse width both-edge specification t tckwl 2.5 2.5 t cyc 8-bit timer timer output delay time t tmod 50 40 ns figure 7.33 timer reset input setup time t tmrs 30 25 ns figure 7.35 timer clock input setup time t tmcs 30 25 ns figure 7.34 timer clock single-edge specification t tmcwh 1.5 1.5 t cyc pulse width both-edge specification t tmcwl 2.5 2.5 t cyc
429 condition a condition b test item symbol min max min max unit conditions wdt overflow output delay time t wovd 50 40 ns figure 7.36 sci input clock asynchronous t scyc 4 4 t cyc figure 7.37 cycle synchronous 6 6 input clock pulse width t sckw 0.4 0.6 0.4 0.6 t scyc input clock rise time t sckr 1.5 1.5 t cyc input clock fall time t sckf 1.5 1.5 transmit data delay time t txd 50 40 ns figure 7.38 receive data setup time (synchronous) t rxs 50 40 ns receive data hold time (synchronous) t rxh 50 40 ns a/d converter trigger input setup time t trgs 30 30 ns figure 7.39
430 7.2.4 a/d conversion characteristics table 7.19 a/d conversion characteristics condition a*: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, = 2 mhz to 20 mhz, t a = 20 c to +75 c (regular specifications), t a = 40 c to +85 c (wide-range specifications) condition b: v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, = 2 mhz to 33 mhz, t a = 20 c to +75 c (regular specifications), t a = 40 c to +85 c (wide-range specifications) * in planning stage condition a condition b item min typ max min typ max unit resolution 10 10 10 10 10 10 bit conversion time 6.7 8.1 s analog input capacitance 20 20 pf permissible signal source impedance 5 5k ? nonlinearity error 7.5 7.5 lsb offset error 7.5 7.5 lsb full-scale error 7.5 7.5 lsb quantization error 0.5 0.5 lsb absolute accuracy 8.0 8.0 lsb
431 7.2.5 d/a conversion characteristics table 7.20 d/a conversion characteristics condition a*: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, = 2 mhz to 20 mhz, t a = 20 c to +75 c (regular specifications), t a = 40 c to +85 c (wide-range specifications) condition b: v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, = 2 mhz to 33 mhz, t a = 20 c to +75 c (regular specifications), t a = 40 c to +85 c (wide-range specifications) * in planning stage condition a condition b item min typ max min typ max unit test conditions resolution 8 8 8 8 8 8 bit conversion time 10 10 s 20 pf capacitive load absolute accuracy 2.0 3.0 2.0 3.0 lsb 2 m ? resistive load 2.0 2.0 lsb 4 m ? resistive load
432 7.2.6 flash memory characteristics table 7.21 flash memory characteristics conditions: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, t a = 0 c to 75 c (program/erase operating temperature range: regular specifications), t a = 0 c to 85 c (program/erase operating temperature range: wide-range specifications) item symbol min typ max unit test conditions programming time * 1, * 2, * 4 t p 10 200 ms/ 128 bytes erase time * 1, * 3, * 6 t e 50 1000 ms/ 128 bytes rewrite times n wec 100 times programming wait time after swe bit setting * 1 x1 s wait time after psu bit setting * 1 y50 s wait time after p bit setting * 1, * 4 zz1 30 s1 n 6 z2 200 s7 n 1000 z3 10 s additional program- ming wait wait time after p bit clearing * 1 5 s wait time after psu bit clearing * 1 5 s wait time after pv bit setting * 1 4 s wait time after h'ff dummy write * 1 2 s wait time after pv bit clearing * 1 2 s wait time after swe bit clearing * 1 100 s maximum number of writes * 1, * 4 n 1000 * 5 times
433 item symbol min typ max unit test conditions erasing wait time after swe bit setting * 1 x1 s wait time after esu bit setting * 1 y 100 s wait time after e bit setting * 1, * 6 z 10 s erase time wait wait time after e bit clearing * 1 10 s wait time after esu bit clearing * 1 10 s wait time after ev bit setting * 1 20 s wait time after h'ff dummy write * 1 2 s wait time after ev bit clearing * 1 4 s wait time after swe bit clearing * 1 100 s maximum number of erases * 1, * 6 n 100 times notes: 1. follow the program/erase algorithms when making the time settings. 3. programming time per 128 bytes. (indicates the total time during which the p bit is set in flash memory control register 1 (flmcr1). does not include the program-verify time.) 3. time to erase one block. (indicates the time during which the e bit is set in flmcr1. does not include the erase-verify time.) 4. maximum programming time t p (max) = wait time after p bit setting (z) n i=1 5. the maximum number of writes (n) should be set as shown below according to the actual set value of (z) so as not to exceed the maximum programming time (t p (max)). the wait time after p bit setting (z) should be changed as follows according to the number of writes (n). number of writes (n) 1 n 6 z = 30 s 7 n 1000 z = 200 s (additional programming) number of writes (n) 1 n 6 z = 10 s 6. for the maximum erase time (t e (max)), the following relationship applies between the wait time after e bit setting (z) and the maximum number of erases (n): t e (max) = wait time after e bit setting (z) maximum number of erases (n)
434 7.3 usage note the f-ztat and mask rom versions both satisfy the electrical characteristics shown in this manual, but actual electrical characteristic values, operating margins, noise margins, and other properties may vary due to differences in manufacturing process, on-chip rom, layout patterns, and so on. when system evaluation testing is carried out using the f-ztat version, the same evaluation testing should also be conducted for the mask rom version when changing over to that version.
435 section 8 registers 8.1 list of registers (address order) table 8.1 list of registers (address order) address abbre- viation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name bus width h'bc00 mra sm1 sm0 dm1 dm0 md1 md0 dts sz dtc 16/32 * 1 to sar bits h'bfff mrb chne disel chns dar cra crb h'fdc0 edsar0 exdmac 16 bits h'fdc1 channel 0 h'fdc2 h'fdc3 h'fdc4 eddar0 h'fdc5 h'fdc6 h'fdc7 h'fdc8 edtcr0 h'fdc9 h'fdca h'fdcb h'fdcc edmdr0 eda bef edrake etende edreqs ams mds1 mds0 h'fdcd edie irf tceie sdir dtsize bgup h'fdce edacr0 sat1 sat0 sarie sara4 sara3 sara2 sara1 sara0 h'fdcf dat1 dat0 darie dara4 dara3 dara2 dara1 dara0 h'fdd0 edsar1 exdmac 16 bits h'fdd1 channel 1 h'fdd2 h'fdd3
436 address abbre- viation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name bus width h'fdd4 eddar1 exdmac 16 bits h'fdd5 channel 1 h'fdd6 h'fdd7 h'fdd8 edtcr1 h'fdd9 h'fdda h'fddb h'fddc edmdr1 eda bef edrake etende edreqs ams mds1 mds0 h'fddd edie irf tceie sdir dtsize bgup h'fdde edacr1 sat1 sat0 sarie sara4 sara3 sara2 sara1 sara0 h'fddf dat1 dat0 darie dara4 dara3 dara2 dara1 dara0 h'fde0 edsar2 exdmac 16 bits h'fde1 channel 2 h'fde2 h'fde3 h'fde4 eddar2 h'fde5 h'fde6 h'fde7 h'fde8 edtcr2 h'fde9 h'fdea h'fdeb h'fdec edmdr2 eda bef edrake etende edreqs ams mds1 mds0 h'fded edie irf tceie sdir dtsize bgup h'fdee edacr2 sat1 sat0 sarie sara4 sara3 sara2 sara1 sara0 h'fdef dat1 dat0 darie dara4 dara3 dara2 dara1 dara0 h'fdf0 edsar3 exdmac 16 bits h'fdf1 channel 3 h'fdf2 h'fdf3 h'fdf4 eddar3 h'fdf5 h'fdf6 h'fdf7
437 address abbre- viation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name bus width h'fdf8 edtcr3 exdmac 16 bits h'fdf9 channel 3 h'fdfa h'fdfb h'fdfc edmdr3 eda bef edrake etende edreqs ams mds1 mds0 h'fdfd edie irf tceie sdir dtsize bgup h'fdfe edacr3 sat1 sat0 sarie sara4 sara3 sara2 sara1 sara0 h'fdff dat1 dat0 darie dara4 dara3 dara2 dara1 dara0 h'fe00 ipra ipra14 ipra13 ipra12 ipra10 ipra9 ipra8 interrupt 16 bits h'fe01 ipra6 ipra5 ipra4 ipra2 ipra1 ipra0 controller h'fe02 iprb iprb14 iprb13 iprb12 iprb10 iprb9 iprb8 h'fe03 iprb6 iprb5 iprb4 iprb2 iprb1 iprb0 h'fe04 iprc iprc14 iprc13 iprc12 iprc10 iprc9 iprc8 h'fe05 iprc6 iprc5 iprc4 iprc2 iprc1 iprc0 h'fe06 iprd iprd14 iprd13 iprd12 iprd10 iprd9 iprd8 h'fe07 iprd6 iprd5 iprd4 iprd2 iprd1 iprd0 h'fe08 ipre ipre14 ipre13 ipre12 ipre10 ipre9 ipre8 h'fe09 ipre6 ipre5 ipre4 ipre2 ipre1 ipre0 h'fe0a iprf iprf14 iprf13 iprf12 iprf10 iprf9 iprf8 h'fe0b iprf6 iprf5 iprf4 iprf2 iprf1 iprf0 h'fe0c iprg iprg14 iprg13 iprg12 iprg10 iprg9 iprg8 h'fe0d iprg6 iprg5 iprg4 iprg2 iprg1 iprg0 h'fe0e iprh iprh14 iprh13 iprh12 iprh10 iprh9 iprh8 h'fe0f iprh6 iprh5 iprh4 iprh2 iprh1 iprh0 h'fe10 ipri ipri14 ipri13 ipri12 ipri10 ipri9 ipri8 h'fe11 ipri6 ipri5 ipri4 ipri2 ipri1 ipri0 h'fe12 iprj iprj14 iprj13 iprj12 iprj10 iprj9 iprj8 h'fe13 iprj6 iprj5 iprj4 iprj2 iprj1 iprj0 h'fe14 iprk iprk14 iprk13 iprk12 iprk10 iprk9 iprk8 h'fe15 iprk6 iprk5 iprk4 iprk2 iprk1 iprk0 h'fe16 itsr its15 its14 its13 its12 its11 its10 its9 its8 h'fe17 its7 its6 its5 its4 its3 its2 its1 its0 h'fe18 ssier ssi15 ssi14 ssi13 ssi12 ssi11 ssi10 ssi9 ssi8 h'fe19 ssi7 ssi6 ssi5 ssi4 ssi3 ssi2 ssi1 ssi0 h'fe1a iscrh irq15scb irq15sca irq14scb irq14sca irq13scb irq13sca irq12scb irq12sca h'fe1b irq11scb irq11sca irq10scb irq10sca irq9scb irq9sca irq8scb irq8sca h'fe1c iscrl irq7scb irq7sca irq6scb irq6sca irq5scb irq5sca irq4scb irq4sca h'fe1d irq3scb irq3sca irq2scb irq2sca irq1scb irq1sca irq0scb irq0sca
438 address abbre- viation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name bus width h'fe1e ircr ire ircks2 ircks1 ircks0 irda 8 bits h'fe20 p1ddr p17ddr p16ddr p15ddr p14ddr p13ddr p12ddr p11ddr p10ddr ports 8 bits h'fe21 p2ddr p27ddr p26ddr p25ddr p24ddr p23ddr p22ddr p21ddr p20ddr h'fe22 p3ddr p35ddr p34ddr p33ddr p32ddr p31ddr p30ddr h'fe24 p5ddr p53ddr p52ddr p51ddr p50ddr h'fe25 p6ddr p65ddr p64ddr p63ddr p62ddr p61ddr p60ddr h'fe26 p7ddr p75ddr p74ddr p73ddr p72ddr p71ddr p70ddr h'fe27 p8ddr p85ddr p84ddr p83ddr p82ddr p81ddr p80ddr h'fe29 paddr pa7ddr pa6ddr pa5ddr pa4ddr pa3ddr pa2ddr pa1ddr pa0ddr h'fe2a pbddr pb7ddr pb6ddr pb5ddr pb4ddr pb3ddr pb2ddr pb1ddr pb0ddr h'fe2b pcddr pc7ddr pc6ddr pc5ddr pc4ddr pc3ddr pc2ddr pc1ddr pc0ddr h'fe2c pdddr pd7ddr pd6ddr pd5ddr pd4ddr pd3ddr pd2ddr pd1ddr pd0ddr h'fe2d peddr pe7ddr pe6ddr pe5ddr pe4ddr pe3ddr pe2ddr pe1ddr pe0ddr h'fe2e pfddr pf7ddr pf6ddr pf5ddr pf4ddr pf3ddr pf2ddr pf1ddr pf0ddr h'fe2f pgddr pg6ddr pg5ddr pg4ddr pg3ddr pg2ddr pg1ddr pg0ddr h'fe32 pfcr0 cs7e cs6e cs5e cs4e cs3e cs2e cs1e cs0e h'fe33 pfcr1 a23e a22e a21e a20e a19e a18e a17e a16e h'fe34 pfcr2 asoe lwroe oes dmacs h'fe36 papcr pa7pcr pa6pcr pa5pcr pa4pcr pa3pcr pa2pcr pa1pcr pa0pcr h'fe37 pbpcr pb7pcr pb6pcr pb5pcr pb4pcr pb3pcr pb2pcr pb1pcr pb0pcr h'fe38 pcpcr pc7pcr pc6pcr pc5pcr pc4pcr pc3pcr pc2pcr pc1pcr pc0pcr h'fe39 pdpcr pd7pcr pd6pcr pd5pcr pd4pcr pd3pcr pd2pcr pd1pcr pd0pcr h'fe3a pepcr pe7pcr pe6pcr pe5pcr pe4pcr pe3pcr pe2pcr pe1pcr pe0pcr h'fe3b h'fe3c p3odr p35odr p34odr p33odr p32odr p31odr p30odr h'fe3d paodr pa7odr pa6odr pa5odr pa4odr pa3odr pa2odr pa1odr pa0odr h'fe80 tcr3 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu3 16 bits h'fe81 tmdr3 bfb bfa md3 md2 md1 md0 h'fe82 tior3h iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'fe83 tior3l iod3 iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 h'fe84 tier3 ttge tciev tgied tgiec tgieb tgiea h'fe85 tsr3 tcfv tgfd tgfc tgfb tgfa h'fe86 tcnt3 h'fe87 h'fe88 tgr3a h'fe89 h'fe8a tgr3b h'fe8b
439 address abbre- viation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name bus width h'fe8c tgr3c tpu3 16 bits h'fe8d h'fe8e tgr3d h'fe8f h'fe90 tcr4 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu4 16 bits h'fe91 tmdr4 md3md2md1md0 h'fe92 tior4 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'fe94 tier4 ttge tcieu tciev tgieb tgiea h'fe95 tsr4 tcfd tcfu tcfv tgfb tgfa h'fe96 tcnt4 h'fe97 h'fe98 tgr4a h'fe99 h'fe9a tgr4b h'fe9b h'fea0 tcr5 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu5 16 bits h'fea1 tmdr5 md3md2md1md0 h'fea2 tior5 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'fea4 tier5 ttge tcieu tciev tgieb tgiea h'fea5 tsr5 tcfd tcfu tcfv tgfb tgfa h'fea6 tcnt5 h'fea7 h'fea8 tgr5a h'fea9 h'feaa tgr5b h'feab h'fec0 abwcr abw7 abw6 abw5 abw4 abw3 abw2 abw1 abw0 bus 16 bits h'fec1 astcr ast7 ast6 ast5 ast4 ast3 ast2 ast1 ast0 controller h'fec2 wtcrah w72 w71 w70 w62 w61 w60 h'fec3 wtcral w52 w51 w50 w42 w41 w40 h'fec4 wtcrbh w32 w31 w30 w22 w21 w20 h'fec5 wtcrbl w12 w11 w10 w02 w01 w00 h'fec6 rdncr rdn7 rdn6 rdn5 rdn4 rdn3 rdn2 rdn1 rdn0 h'fec8 csacrh csxh7 csxh6 csxh5 csxh4 csxh3 csxh2 csxh1 csxh0 h'fec9 csacrl csxt7 csxt6 csxt5 csxt4 csxt3 csxt2 csxt1 csxt0 h'feca bromcrh bsrm0 bsts02 bsts01 bsts00 bswd01 bswd00 h'fecb bromcrl bsrm1 bsts12 bsts11 bsts10 bswd11 bswd10
440 address abbre- viation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name bus width h'fecc bcr brle breq0e idlc icis1 icis0 wdbe waite bus 16 bits h'fecd controller h'fece * 8 ramer rams ram2 ram1 ram0 rom 16 bits h'fed0 dramcr 0ee rast cast rmts2 rmts1 rmts0 bus 16 bits h'fed1 be rcdm dds edds mxc2 mxc1 mxc0 controller h'fed2 draccr drmi tpc1 tpc0 rcd1 rcd0 h'fed3 h'fed4 refcr cmf cmie rcw1 rcw0 rtck2 rtck1 rtck0 h'fed5 rfshe cbrm rlw1 rlw0 slfrf tpcs2 tpcs1 tpcs0 h'fed6 rtcnt h'fed7 rtcor h'fee0 mar0ah dmac 16 bits h'fee1 h'fee2 mar0al h'fee3 h'fee4 ioar0a h'fee5 h'fee6 etcr0a h'fee7 h'fee8 mar0bh h'fee9 h'feea mar0bl h'feeb h'feec ioar0b h'feed h'feee etcr0b h'feef h'fef0 mar1ah h'fef1 h'fef2 mar1al h'fef3 h'fef4 ioar1a h'fef5 h'fef6 etcr1a h'fef7 h'fef8 mar1bh h'fef9
441 address abbre- viation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name bus width h'fefa mar1bl dmac 16 bits h'fefb h'fefc ioar1b h'fefd h'fefe etcr1b h'feff h'ff20 dmawer we1b we1a we0b we0a 8 bits h'ff21 dmatcr tee1 tee0 h'ff22 dmacr0a dtsz dtid rpe dtdir dtf3 dtf2 dtf1 dtf0 short address mode 16 bits dtsz said saide blkdir blke full address mode h'ff23 dmacr0b dtsz dtid rpe dtdir dtf3 dtf2 dtf1 dtf0 short address mode daid daide dtf3 dtf2 dtf1 dtf0 full address mode h'ff24 dmacr1a dtsz dtid rpe dtdir dtf3 dtf2 dtf1 dtf0 short address mode dtsz said saide blkdir blke full address mode h'ff25 dmacr1b dtsz dtid rpe dtdir dtf3 dtf2 dtf1 dtf0 short address mode daid daide dtf3 dtf2 dtf1 dtf0 full address mode h'ff26 dmabcrh fae1 fae0 sae1 sae0 dta1b dta1a dta0b dta0a short address mode fae1 fae0 dta1 dta0 full address mode
442 address abbre- viation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name bus width h'ff27 dmabcrl dte1b dte1a dte0b dte0a dtie1b dtie1a dtie0b dtie0a short address mode 16 bits dtme1 dte1 dtme0 dte0 dtie1b dtie1a dtie0b dtie0a full address mode h'ff28 to h'ff2f dtcer dtce7 dtce6 dtce5 dtce4 dtce3 dtce2 dtce1 dtce0 dtc 16 bits h'ff30 dtvecr swdte dtvec6 dtvec5 dtvec4 dtvec3 dtvec2 dtvec1 dtvec0 interrupt 16 bits h'ff31 intcr intm1 intm0 nmieg controller h'ff32 ier irq15e irq14e irq13e irq12e irq11e irq10e irq9e irq8e h'ff33 irq7e irq6e irq5e irq4e irq3e irq2e irq1e irq0e h'ff34 isr irq15f irq14f irq13f irq12f irq11f irq10f irq9f irq8f h'ff35 irq7f irq6f irq5f irq4f irq3f irq2f irq1f irq0f h'ff3a sbycr ssby ope sts3 sts2 sts1 sts0 system 8 bits h'ff3b sckcr pstop stcs sck2 sck1 sck0 controller h'ff3d syscr macs flshe expe rame h'ff3e mdcr mds2 mds1 mds0 h'ff40 mstpcrh acse mstp14 mstp13 mstp12 mstp11 mstp10 mstp9 mstp8 h'ff41 mstpcrl mstp7 mstp6 mstp5 mstp4 mstp3 mstp2 mstp1 mstp0 h'ff45 pllcr 000000 stc1 stc0 h'ff46 pcr g3cms1 g3cms0 g2cms1 g2cms0 g1cms1 g1cms0 g0cms1 g0cms0 ppg 8 bits h'ff47 pmr g3inv g2inv g1inv g0inv g3nov g2nov g1nov g0nov h'ff48 nderh nder15 nder14 nder13 nder12 nder11 nder10 nder9 nder8 h'ff49 nderl nder7 nder6 nder5 nder4 nder3 nder2 nder1 nder0 h'ff4a podrh pod15 pod14 pod13 pod12 pod11 pod10 pod9 pod8 h'ff4b podrl pod7 pod6 pod5 pod4 pod3 pod2 pod1 pod0 h'ff4c * 2 ndrh ndr15 ndr14 ndr13 ndr12 ndr11 ndr10 ndr9 ndr8 h'ff4d * 2 ndrl ndr7 ndr6 ndr5 ndr4 ndr3 ndr2 ndr1 ndr0 h'ff4e * 2 ndrh ndr11 ndr10 ndr9 ndr8 h'ff4f * 2 ndrl ndr3 ndr2 ndr1 ndr0 h'ff50 port1 p17 p16 p15 p14 p13 p12 p11 p10 ports 8 bits h'ff51 port2 p27 p26 p25 p24 p23 p22 p21 p20 h'ff52 port3 p35 p34 p33 p32 p31 p30 h'ff53 port4 p47 p46 p45 p44 p43 p42 p41 p40 h'ff54 port5 p57 p56 p55 p54 p53 p52 p51 p50 h'ff55 port6 p65 p64 p63 p62 p61 p60 h'ff56 port7 p75 p74 p73 p72 p71 p70 h'ff57 port8 p85 p84 p83 p82 p81 p80
443 address abbre- viation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name bus width h'ff59 porta pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 ports 8 bits h'ff5a portb pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 h'ff5b portc pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 h'ff5c portd pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 h'ff5d porte pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 h'ff5e portf pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 h'ff5f portg pg6 pg5 pg4 pg3 pg2 pg1 pg0 h'ff60 p1dr p17dr p16dr p15dr p14dr p13dr p12dr p11dr p10dr h'ff61 p2dr p27dr p26dr p25dr p24dr p23dr p22dr p21dr p20dr h'ff62 p3dr p35dr p34dr p33dr p32dr p31dr p30dr h'ff64 p5dr p53dr p52dr p51dr p50dr h'ff65 p6dr p65dr p64dr p63dr p62dr p61dr p60dr h'ff66 p7dr p75dr p74dr p73dr p72dr p71dr p70dr h'ff67 p8dr p85dr p84dr p83dr p82dr p81rd p80dr h'ff69 padr pa7dr pa6dr pa5dr pa4dr pa3dr pa2dr pa1dr pa0dr h'ff6a pbdr pb7dr pb6dr pb5dr pb4dr pb3dr pb2dr pb1dr pb0dr h'ff6b pcdr pc7dr pc6dr pc5dr pc4dr pc3dr pc2dr pc1dr pc0dr h'ff6c pddr pd7dr pd6dr pd5dr pd4dr pd3dr pd2dr pd1dr pd0dr h'ff6d pedr pe7dr pe6dr pe5dr pe4dr pe3dr pe2dr pe1dr pe0dr h'ff6e pfdr pf7dr pf6dr pf5dr pf4dr pf3dr pf2dr pf1dr pf0dr h'ff6f pgdr pg6dr pg5dr pg4dr pg3dr pg2dr pg1dr pg0dr h'ff70 porth ph3ph2ph1ph0 h'ff72 phdr ph3dr ph2dr ph1dr ph0dr h'ff74 phddr ph3ddr ph2ddr ph1ddr ph0ddr h'ff78 smr0 c/ a / gm * 3 chr/ blk * 4 pe o/ e stop/ bcp1 * 5 m p / b cp 0 * 6 cks1 cks0 sci0, smart card 8 bits h'ff79 brr0 interface 0 h'ff7a scr0 tie rie te re mpie teie cke1 cke0 h'ff7b tdr0 h'ff7c ssr0 tdre rdrf orer fer/ ers * 7 per tend mpb mpbt h'ff7d rdr0 h'ff7e scmr0 sdir sinv smif h'ff80 smr1 c/ a / gm * 3 chr/ blk * 4 pe o/ e stop/ bcp1 * 5 mp/ bcp0 * 6 cks1 cks0 sci1, smart card 8 bits h'ff81 brr1 interface 1 h'ff82 scr1 tie rie te re mpie teie cke1 cke0 h'ff83 tdr1
444 address abbre- viation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name bus width h'ff84 ssr1 tdre rdrf orer fer/ ers * 7 per tend mpb mpbt sci1, smart card 8 bits h'ff85 rdr1 interface 1 h'ff86 scmr1 sdir sinv smif h'ff88 smr2 c/ a / gm * 3 chr/ blk * 4 pe o/ e stop/ bcp1 * 5 mp/ bcp0 * 6 cks1 cks0 sci2, smart card 8 bits h'ff89 brr2 interface 2 h'ff8a scr2 tie rie te re mpie teie cke1 cke0 h'ff8b tdr2 h'ff8c ssr2 tdre rdrf orer fer/ ers * 7 per tend mpb mpbt h'ff8d rdr2 h'ff8e scmr2 sdir sinv smif h'ff90 addrah ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 a/d 8 bits h'ff91 addral ad1 ad0 converter h'ff92 addrbh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'ff93 addrbl ad1 ad0 h'ff94 addrch ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'ff95 addrcl ad1 ad0 h'ff96 addrdh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'ff97 addrdl ad1 ad0 h'ff98 adcsr adf adie adst scan cks ch2 ch1 ch0 h'ff99 adcr trgs1 trgs0 cks1 ch3 h'ffa4 dadr0 d/a 8 bits h'ffa5 dadr1 h'ffa6 dacr01 daoe1 daoe0 dae h'ffa8 dadr2 h'ffa9 dadr3 h'ffaa dacr23 daoe1 daoe0 dae h'ffb0 tcr0 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 8-bit timer 16 bits h'ffb1 tcr1 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 channel 0, 1 h'ffb2 tcsr0 cmfb cmfa ovf adte os3 os2 os1 os0 h'ffb3 tcsr1 cmfb cmfa ovf os3 os2 os1 os0 h'ffb4 tcora0 h'ffb5 tcora1 h'ffb6 tcorb0 h'ffb7 tcorb1 h'ffb8 tcnt0 h'ffb9 tcnt1
445 address abbre- viation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name bus width h'ffbc (read) tcsr ovf wt/ it tme cks2 cks1 cks0 watchdog timer 16 bits h'ffbd (read) tcnt h'ffbf (read) rstcsr wovf rste h'ffc0 tstr cst5 cst4 cst3 cst2 cst1 cst0 tpu 16 bits h'ffc1 tsyr sync5 sync4 sync3 sync2 sync1 sync0 h'ffc8 flmcr1 * 8 fwe swe esu psu ev pv e p flash 8 bits h'ffc9 flmcr2 * 8 fler ?supsu h'ffca ebr1 * 8 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 h'ffcb ebr2 * 8 eb10 eb9 eb8 h'ffd0 tcr0 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu0 16 bits h'ffd1 tmdr0 bfb bfa md3 md2 md1 md0 h'ffd2 tior0h iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'ffd3 tior0l iod3 iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 h'ffd4 tier0 ttge tciev tgied tgiec tgieb tgiea h'ffd5 tsr0 tcfv tgfd tgfc tgfb tgfa h'ffd6 tcnt0 h'ffd7 h'ffd8 tgr0a h'ffd9 h'ffda tgr0b h'ffdb h'ffdc tgr0c h'ffdd h'ffde tgr0d h'ffdf h'ffe0 tcr1 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu1 16 bits h'ffe1 tmdr1 md3md2md1md0 h'ffe2 tior1 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'ffe4 tier1 ttge tcieu tciev tgieb tgiea h'ffe5 tsr1 tcfd tcfu tcfv tgfb tgfa h'ffe6 tcnt1 h'ffe7 h'ffe8 tgr1a h'ffe9 h'ffea tgr1b h'ffeb
446 address abbre- viation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name bus width h'fff0 tcr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu2 16 bits h'fff1 tmdr2 md3md2md1md0 h'fff2 tior2 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'fff4 tier2 ttge tcieu tciev tgieb tgiea h'fff5 tsr2 tcfd tcfu tcfv tgfb tgfa h'fff6 tcnt2 h'fff7 h'fff8 tgr2a h'fff9 h'fffa tgr2b h'fffb notes: 1. located in on-chip ram. the bus width is 32 bits when the dtc accesses this area as register information, and 16 bits otherwise. 2. if the pulse output group 2 and pulse output group 3 output triggers are the same according to the pcr setting, the ndrh address will be h'ff4c, and if different, the address of ndrh for group 2 will be h'ff4e, and that for group 3 will be h'ff4c. similarly, if the pulse output group 0 and pulse output group 1 output triggers are the same according to the pcr setting, the ndrl address will be h'ff4d, and if different, the address of ndrl for group 0 will be h'ff4f, and that for group 1 will be h'ff4d. 3. functions as c/ a for sci use, and as gm for smart card interface use. 4. functions as chr for sci use, and as blk for smart card interface use. 5. functions as stop for sci use, and as bcp1 for smart card interface use. 6. functions as mp for sci use, and as bcp0 for smart card interface use. 7. functions as fer for sci use, and as ers for smart card interface use. 8. valid only in f-ztat version
447 8.2 list of registers (by module) table 8.2 list of registers (by module) module register abbreviation r/w initial value address * 1 interrupt interrupt control register intcr r/w h'00 h'ff31 controller irq sense control register h iscrh r/w h'0000 h'ff1a irq sense control register l iscrl r/w h'0000 h'ff1c irq enable register ier r/w h'0000 h'ff32 irq status register isr r/(w) * 2 h'0000 h'ff34 irq pin select register itsr r/w h'0000 h'fe16 software standby clearing irq enable register ssier r/w h'0007 h'fe18 interrupt priority register a ipra r/w h'7777 h'fe00 interrupt priority register b iprb r/w h'7777 h'fe02 interrupt priority register c iprc r/w h'7777 h'fe04 interrupt priority register d iprd r/w h'7777 h'fe06 interrupt priority register e ipre r/w h'7777 h'fe08 interrupt priority register f iprf r/w h'7777 h'fe0a interrupt priority register g iprg r/w h'7777 h'fe0c interrupt priority register h iprh r/w h'7777 h'fe0e interrupt priority register i ipri r/w h'7777 h'fe10 interrupt priority register j iprj r/w h'7777 h'fe12 interrupt priority register k iprk r/w h'7777 h'fe14 dmac memory address register 0a mar0a r/w undefined h'fee0 channel 0 i/o address register 0a ioar0a r/w undefined h'fee4 execute transfer count register 0a etcr0a r/w undefined h'fee6 memory address register 0b mar0b r/w undefined h'fee8 i/o address register 0b ioar0b r/w undefined h'feec execute transfer count register 0b etcr0b r/w undefined h'feee dmac memory address register 1a mar1a r/w undefined h'fef0 channel 1 i/o address register 1a ioar1a r/w undefined h'fef4 execute transfer count register 1a etcr1a r/w undefined h'fef6 memory address register 1b mar1b r/w undefined h'fef8 i/o address register 1b ioar1b r/w undefined h'fefc execute transfer count register 1b etcr1b r/w undefined h'fefe
448 module register abbreviation r/w initial value address * 1 dmac dma write enable register dmawer r/w h'00 h'ff20 channels 0 dma terminal control register dmatcr r/w h'00 h'ff21 and 1 dma control register 0a dmacr0a r/w h'00 h'ff22 dma control register 0b dmacr0b r/w h'00 h'ff23 dma control register 1a dmacr1a r/w h'00 h'ff24 dma control register 1b dmacr1b r/w h'00 h'ff25 dma band control register dmabcr r/w h'0000 h'ff26 module stop control register mstpcr r/w h'0fff h'ff40 dtc dtc mode register a mra * 3 undefined * 4 dtc mode register b mrb * 3 undefined * 4 dtc source address register sar * 3 undefined * 4 dtc destination address register dar * 3 undefined * 4 dtc transfer count register a cra * 3 undefined * 4 dtc transfer count register b crb * 3 undefined * 4 dtc enable register dtcer r/w h'00 h'ff28 to h'ff2f dtc vector register dtvecr r/w h'00 h'ff30 module stop control register mstpcr r/w h'0fff h'ff40 exdmac exdma source address register 0 edsar0 r/w undefined h'fdc0 channel 0 exdma destination address register 0 eddar0 r/w undefined h'fdc4 exdma transfer count register 0 edtcr0 r/w undefined h'fdc8 exdma mode control register 0 edmdr0 r/w * 5 h'0000 h'fdcc exdma address control register 0 edacr0 r/w h'0000 h'fdce exdmac exdma source address register 1 edsar1 r/w undefined h'fdd0 channel 1 exdma destination address register 1 eddar1 r/w undefined h'fdd4 exdma transfer count register 1 edtcr1 r/w undefined h'fdd8 exdma mode control register 1 edmdr1 r/w * 5 h'0000 h'fddc exdma address control register 1 edacr1 r/w h'0000 h'fdde
449 module register abbreviation r/w initial value address * 1 exdmac exdma source address register 2 edsar2 r/w undefined h'fde0 channel 2 exdma destination address register 2 eddar2 r/w undefined h'fde4 exdma transfer count register 2 edtcr2 r/w undefined h'fde8 exdma mode control register 2 edmdr2 r/w * 5 h'0000 h'fdec exdma address control register 2 edacr2 r/w h'0000 h'fdee exdmac exdma source address register 3 edsar3 r/w undefined h'fdf0 channel 3 exdma destination address register 3 eddar3 r/w undefined h'fdf4 exdma transfer count register 3 edtcr3 r/w undefined h'fdf8 exdma mode control register 3 edmdr3 r/w * 5 h'0000 h'fdfc exdma address control register 3 edacr3 r/w h'0000 h'fdfe all exdmac channels module stop control register mstpcr r/w h'0fff h'ff40 bus bus width control register abwcr r/w h'ff/h'00 * 6 h'fec0 controller access state control register astcr r/w h'ff h'fec1 wait control register a wtcra r/w h'7777 h'fec2 wait control register b wtcrb r/w h'7777 h'fec4 read strobe timing control register rdncr r/w h'00 h'fec6 chip select assertion period control csacrh r/w h'00 h'fec8 register csacrl r/w h'00 h'fec9 burst rom interface control bromcrh r/w h'00 h'feca register bromcrl r/w h'00 h'fecb bus control register bcr r/w h'1c00 h'fecc dram control register dramcr r/w h'0000 h'fed0 dram access control register draccr r/w h'00 h'fed2 refresh control register refcr r/w h'0000 h'fed4 refresh timer counter rtcnt r/w h'00 h'fed6 refresh time constant register rtcor r/w h'ff h'fed7 tpu0 timer control register 0 tcr0 r/w h'00 h'ffd0 timer mode register 0 tmdr0 r/w h'c0 h'ffd1 timer i/o control register 0h tior0h r/w h'00 h'ffd2 timer i/o control register 0l tior0l r/w h'00 h'ffd3
450 module register abbreviation r/w initial value address * 1 tpu0 timer interrupt enable register 0 tier0 r/w h'40 h'ffd4 timer status register 0 tsr0 r/(w) * 2 h'c0 h'ffd5 timer counter 0 tcnt0 r/w h'0000 h'ffd6 timer general register 0a tgr0a r/w h'ffff h'ffd8 timer general register 0b tgr0b r/w h'ffff h'ffda timer general register 0c tgr0c r/w h'ffff h'ffdc timer general register 0d tgr0d r/w h'ffff h'ffde tpu1 timer control register 1 tcr1 r/w h'00 h'ffe0 timer mode register 1 tmdr1 r/w h'c0 h'ffe1 timer i/o control register 1 tior1 r/w h'00 h'ffe2 timer interrupt enable register 1 tier1 r/w h'40 h'ffe4 timer status register 1 tsr1 r/(w) * 2 h'c0 h'ffe5 timer counter 1 tcnt1 r/w h'0000 h'ffe6 timer general register 1a tgr1a r/w h'ffff h'ffe8 timer general register 1b tgr1b r/w h'ffff h'ffea tpu2 timer control register 2 tcr2 r/w h'00 h'fff0 timer mode register 2 tmdr2 r/w h'c0 h'fff1 timer i/o control register 2 tior2 r/w h'00 h'fff2 timer interrupt enable register 2 tier2 r/w h'40 h'fff4 timer status register 2 tsr2 r/(w) * 2 h'c0 h'fff5 timer counter 2 tcnt2 r/w h'0000 h'fff6 timer general register 2a tgr2a r/w h'ffff h'fff8 timer general register 2b tgr2b r/w h'ffff h'fffa tpu3 timer control register 3 tcr3 r/w h'00 h'fe80 timer mode register 3 tmdr3 r/w h'c0 h'fe81 timer i/o control register 3h tior3h r/w h'00 h'fe82 timer i/o control register 3l tior3l r/w h'00 h'fe83 timer interrupt enable register 3 tier3 r/w h'40 h'fe84 timer status register 3 tsr3 r/(w) * 2 h'c0 h'fe85 timer counter 3 tcnt3 r/w h'0000 h'fe86 timer general register 3a tgr3a r/w h'ffff h'fe88 timer general register 3b tgr3b r/w h'ffff h'fe8a
451 module register abbreviation r/w initial value address * 1 tpu3 timer general register 3c tgr3c r/w h'ffff h'fe8c timer general register 3d tgr3d r/w h'ffff h'fe8e tpu4 timer control register 4 tcr4 r/w h'00 h'fe90 timer mode register 4 tmdr4 r/w h'c0 h'fe91 timer i/o control register 4 tior4 r/w h'00 h'fe92 timer interrupt enable register 4 tier4 r/w h'40 h'fe94 timer status register 4 tsr4 r/(w) * 2 h'c0 h'fe95 timer counter 4 tcnt4 r/w h'0000 h'fe96 timer general register 4a tgr4a r/w h'ffff h'fe98 timer general register 4b tgr4b r/w h'ffff h'fe9a tpu5 timer control register 5 tcr5 r/w h'00 h'fea0 timer mode register 5 tmdr5 r/w h'c0 h'fea1 timer i/o control register 5 tior5 r/w h'00 h'fea2 timer interrupt enable register 5 tier5 r/w h'40 h'fea4 timer status register 5 tsr5 r/(w) * 2 h'c0 h'fea5 timer counter 5 tcnt5 r/w h'0000 h'fea6 timer general register 5a tgr5a r/w h'ffff h'fea8 timer general register 5b tgr5b r/w h'ffff h'feaa all tpu timer start register tstr r/w h'00 h'ffc0 channels timer sync register tsyr r/w h'00 h'ffc1 module stop control register mstpcr r/w h'0fff h'ff40 ppg ppg output control register pcr r/w h'ff h'ff46 ppg output mode register pmr r/w h'f0 h'ff47 next data enable register h nderh r/w h'00 h'ff48 next data enable register l nderl r/w h'00 h'ff49 output data register h podrh r/(w) * 7 h'00 h'ff4a output data register l podrl r/(w) * 7 h'00 h'ff4b next data register h ndrh r/w h'00 h'ff4c * 8 h'ff4e next data register l ndrl r/w h'00 h'ff4d * 8 h'ff4f port 1 data direction register p1ddr w h'00 h'fe20 port 2 data direction register p2ddr w h'00 h'fe21 module stop control register mstpcr r/w h'0fff h'ff40
452 module register abbreviation r/w initial value address * 1 8-bit timer timer control register 0 tcr0 r/w h'00 h'ffb0 0 timer control/status register 0 tcsr0 r/(w) * 9 h'00 h'ffb2 timer constant register a0 tcora0 r/w h'ff h'ffb4 timer constant register b0 tcorb0 r/w h'ff h'ffb6 timer counter 0 tcnt0 r/w h'00 h'ffb8 8-bit timer timer control register 1 tcr1 r/w h'00 h'ffb1 1 timer control/status register 1 tcsr1 r/(w) * 9 h'10 h'ffb3 timer constant register a1 tcora1 r/w h'ff h'ffb5 timer constant register b1 tcorb1 r/w h'ff h'ffb7 timer counter 1 tcnt1 r/w h'00 h'ffb9 both 8-bit timer channels module stop control register mstpcr r/w h'0fff h'ff40 wdt timer control/status register tcsr r/(w) * 11 h'18 h'ffbc * 10 timer counter tcnt r/w h'00 h'ffbc : write * 10 h'ffbd : read reset control/status register rstcsr r/(w) * 11 h'1f h'ffbe : write * 10 h'ffbf : read sci0 serial mode register 0 smr0 r/w h'00 h'ff78 bit rate register 0 brr0 r/w h'ff h'ff79 serial control register 0 scr0 r/w h'00 h'ff7a transmit data register 0 tdr0 r/w h'ff h'ff7b serial status register 0 ssr0 r/(w) * 2 h'84 h'ff7c receive data register 0 rdr0 r h'00 h'ff7d smart card mode register 0 scmr0 r/w h'f2 h'ff7e irda control register ircr r/w h'00 h'fe1e sci1 serial mode register 1 smr1 r/w h'00 h'ff80 bit rate register 1 brr1 r/w h'ff h'ff81 serial control register 1 scr1 r/w h'00 h'ff82
453 module register abbreviation r/w initial value address * 1 sci1 transmit data register 1 tdr1 r/w h'ff h'ff83 serial status register 1 ssr1 r/(w) * 2 h'84 h'ff84 receive data register 1 rdr1 r h'00 h'ff85 smart card mode register 1 scmr1 r/w h'f2 h'ff86 sci2 serial mode register 2 smr2 r/w h'00 h'ff88 bit rate register 2 brr2 r/w h'ff h'ff89 serial control register 2 scr2 r/w h'00 h'ff8a transmit data register 2 tdr2 r/w h'ff h'ff8b serial status register 2 ssr2 r/(w) * 2 h'84 h'ff8c receive data register 2 rdr2 r h'00 h'ff8d smart card mode register 2 scmr2 r/w h'f2 h'ff8e all sci channels module stop control register mstpcr r/w h'0fff h'ff40 adc a/d data register ah addrah r h'00 h'ff90 a/d data register al addral r h'00 h'ff91 a/d data register bh addrbh r h'00 h'ff92 a/d data register bl addrbl r h'00 h'ff93 a/d data register ch addrch r h'00 h'ff94 a/d data register cl addrcl r h'00 h'ff95 a/d data register dh addrdh r h'00 h'ff96 a/d data register dl addrdl r h'00 h'ff97 a/d control/status register adcsr r/(w) * 11 h'00 h'ff98 a/d control register adcr r/w h'3f h'ff99 module stop control register mstpcr r/w h'0fff h'ff40 dac0, 1 d/a data register 0 dadr0 r/w h'00 h'ffa4 d/a data register 1 dadr1 r/w h'00 h'ffa5 d/a control register 01 dacr01 r/w h'1f h'ffa6 dac2, 3 d/a data register 2 dadr2 r/w h'00 h'ffa8 d/a data register 3 dadr3 r/w h'00 h'ffa9 d/a control register 23 dacr23 r/w h'1f h'ffaa all dac channels module stop control register mstpcr r/w h'0fff h'ff40
454 module register abbreviation r/w initial value address * 1 on-chip ram system control register syscr r/w h'81 h'ff3d flash flash memory control register 1 flmcr1 * 16 r/w * 13 h'00 * 14 h'ffc8 * 12 memory flash memory control register 2 flmcr2 * 16 r/w * 13 h'00 * 15 h'ffc9 * 12 erase block register 1 ebr1 * 16 r/w * 13 h'00 * 15 h'ffca * 12 erase block register 2 ebr2 * 16 r/w * 13 h'00 * 15 h'ffcb * 12 ram emulation register ramer r/w h'00 h'fece * 18 system standby control register sbycr r/w h'0f h'ff3a control system clock control register sckcr r/w h'00 h'ff3b system control register syscr r/w undefined h'ff3d mode control register mdcr r undefined h'ff3e module stop control register h mstpcrh r/w h'0f h'ff40 module stop control register l mstpcrl r/w h'ff h'ff41 pll control register pllcr r/w h'00 h'ff45 software standby clearing irq enable register ssier r/w h'0007 h'fe18 power- standby control register sbycr r/w h'0f h'ff3a down state system clock control register sckcr r/w h'00 h'ff3b module stop control register h mstpcrh r/w h'0f h'ff40 module stop control register l mstpcrl r/w h'ff h'ff41 software standby clearing irq enable register ssier r/w h'ff h'fe18 port 1 port 1 data direction register p1ddr w h'00 h'fe20 port 1 data register p1dr r/w h'00 h'ff60 port 1 register port1 r undefined h'ff50 port 2 port 2 data direction register p2ddr w h'00 h'fe21 port 2 data register p2dr r/w h'00 h'ff61 port 2 register port2 r undefined h'ff51 port 3 port 3 data direction register p3ddr w h'00 h'fe22 port 3 data register p3dr r/w h'00 h'ff62 port 3 register port3 r undefined h'ff52 port 3 open drain control register p3odr r/w h'00 h'fe3c port 4 port 4 register port4 r undefined h'ff53 port function control register 2 pfcr2 r/w h'0e h'fe34
455 module register abbreviation r/w initial value address * 1 port 5 port 5 data direction register p5ddr w h'00 h'fe24 port 5 data register p5dr r/w h'00 h'ff64 port 5 register port5 r undefined h'ff54 port 6 port 6 data direction register p6ddr w h'00 h'fe25 port 6 data register p6dr r/w h'00 h'ff65 port 6 register port6 r undefined h'ff55 port function control register 2 pfcr2 r/w h'0e h'fe34 port 7 port 7 data direction register p7ddr w h'00 h'fe26 port 7 data register p7dr r/w h'00 h'ff66 port 7 register port7 r undefined h'ff56 port function control register 2 pfcr2 r/w h'00 h'fe34 port 8 port 8 data direction register p8ddr w h'00 h'fe27 port 8 data register p8dr r/w h'00 h'ff67 port 8 register port8 r undefined h'ff57 port a port a data direction register paddr w h'00 h'fe29 port a data register padr r/w h'00 h'ff69 port a register porta r undefined h'ff59 port a mos pull-up control register papcr r/w h'00 h'fe36 port a open drain control register paodr r/w h'00 h'fe3d port function control register 1 pfcr1 r/w h'ff h'fe33 port b port b data direction register pbddr w h'00 h'fe2a port b data register pbdr r/w h'00 h'ff6a port b register portb r undefined h'ff5a port b mos pull-up control register pbpcr r/w h'00 h'fe37 port c port c data direction register pcddr w h'00 h'fe2b port c data register pcdr r/w h'00 h'ff6b port c register portc r undefined h'ff5b port c mos pull-up control register pcpcr r/w h'00 h'fe38 port d port d data direction register pdddr w h'00 h'fe2c port d data register pddr r/w h'00 h'ff6c port d register portd r undefined h'ff5c port d mos pull-up control register pdpcr r/w h'00 h'fe39
456 module register abbreviation r/w initial value address * 1 port e port e data direction register peddr w h'00 h'fe2d port e data register pedr r/w h'00 h'ff6d port e register porte r undefined h'ff5d port e mos pull-up control register pepcr r/w h'00 h'fe3a port f port f data direction register pfddr w h'80/h'00 * 17 h'fe2e port f data register pfdr r/w h'00 h'ff6e port f register portf r undefined h'ff5e port function control register 2 pfcr2 r/w h'0e h'fe34 port g port g data direction register pgddr w h'01/h'00 * 17 h'fe2f port g data register pgdr r/w h'00 h'ff6f port g register portg r undefined h'ff5f port function control register 0 pfcr0 r/w h'ff h'fe32 port h port h data direction register phddr w h'00 h'ff74 port h data register phdr r/w h'00 h'ff72 port h register porth r undefined h'ff70 port function control register 0 pfcr0 r/w h'ff h'fe32 port function control register 2 pfcr2 r/w h'0e h'fe34 notes: 1. lower 16 bits of the address. 2. only 0 can be written for flag clearing. 3. registers in the dtc cannot be read or written to directly. 4. located as register information in on-chip ram addresses h'bc00 to h'bfff. cannot be located in external memory space. do not clear the rame bit in syscr to 0 when using the dtc. 5. the value written in bit 15 of edmdr0 to edmdr3 may not be effective immediately. bits 14 and 6 of edmdr0 to edmdr3 can only be written with 0 after being read as 1, to clear the flags. 6. determined by the mcu operating mode. 7. bits used for pulse output cannot be written to. 8. if the pulse output group 2 and pulse output group 3 output triggers are the same according to the pcr setting, the ndrh address will be h'ff4c, and if different, the address of ndrh for group 2 will be h'ff4e, and that for group 3 will be h'ff4c. similarly, if the pulse output group 0 and pulse output group 1 output triggers are the same according to the pcr setting, the ndrl address will be h'ff4d, and if different, the address of ndrl for group 0 will be h'ff4f, and that for group 1 will be h'ff4d. 9. only 0 can be written to bits 7 to 5, to clear the flags. 10. for information on writing, see section 11.2.4, notes on register access, in the h8s/2678 series hardware manual. 11. only 0 can be written to bit 7, to clear the flag.
457 12. flash memory registers are allocated to the same addresses as other registers. register selection is performed by means of the flshe bit in the system control register (syscr). 13. in modes in which the on-chip flash memory is disabled, a read will return h'00, and writes are invalid. writes are also disabled when the fwe bit in flmcr1 is cleared to 0. 14. when a high level is input to the fwe pin, the initial value is h'80. 15. when a low level is input to the fwe pin, or if a high level is input but the swe bit in flmcr1 is not set, these registers are initialized to h'00. 16. flmcr1, flmcr2, ebr1, and ebr2 are 8-bit registers. only byte access can be used on these registers, with the access requiring two states. 17. the initial value depends on the mode. 18. valid in the f-ztat version only.
458 8.3 register descriptions dacr01?/a control register 01 h'ffa6 d/a converter register name address to which the register is mapped name of on-chip supporting module register acronym bit numbers initial bit values names of the bits. dashes (? indicate reserved bits. full name of bit descriptions of bit settings read only write only read and write r w r/w possible types of access bit initial value read/write 7 daoe1 0 r/w 6 daoe0 0 r/w 5 dae 0 r/w 4 1 3 1 0 1 2 1 1 1 * : don? care d/a output enable 0 0 da0 analog output disabled 1 channel 0 d/a conversion enabled. da0 analog output enabled d/a output enable 1 0 da1 analog output disabled 1 channel 1 d/a conversion enabled. da1 analog output enabled d/a conversion control 0 channel 0 and 1 d/a conversion disabled daoe0 description 1 channel 0 d/a conversion enabled * dae 0 0 daoe1 channel 1 d/a conversion disabled channel 0 and 1 d/a conversion enabled 1 0 channel 0 d/a conversion disabled 0 1 channel 1 d/a conversion enabled channel 0 and 1 d/a conversion enabled 1 1 channel 0 and 1 d/a conversion enabled *
459 mra?tc mode register a h'bc00 to h'bfff dtc bit initial value read/write 7 sm1 undefined 6 sm0 undefined 5 dm1 undefined 4 dm0 undefined 3 md1 undefined 2 md0 undefined 1 dts undefined 0 sz undefined 0 byte-size transfer word-size transfer dtc data transfer size 1 0 destination is repeat area or block area source is repeat area or block area dtc transfer mode select 1 0 0 normal mode repeat mode dtc mode (md1, md0) 1 10 1 block transfer mode 0 dar is fixed destination address mode 10 1 dar is incremented after a transfer (+1 when sz = 0, +2 when sz = 1) dar is decremented after a transfer ( 1 when sz = 0, 2 when sz = 1) 0 sar is fixed source address mode 10 1 sar is incremented after a transfer (+1 when sz = 0, +2 when sz = 1) sar is decremented after a transfer ( 1 when sz = 0, 2 when sz = 1)
460 mrb?tc mode register b h'bc00 to h'bfff dtc bit initial value read/write 7 chne undefined 6 disel undefined 5 chns undefined 4 undefined 3 undefined 2 undefined 1 undefined 0 undefined 0 after a data transfer ends, the cpu interrupt is disabled unless the transfer counter is 0 after a data transfer ends, the cpu interrupt is enabled dtc interrupt select 1 0 dtc data transfer finished (waiting for activation) dtc chain transfer (new register information is read, and data transfer performed) dtc chain transfer enable 1 reserved bits (write 0) dtc chain transfer select chne 0 description 1 1 chns 0 1 no chain transfer (activation-standby state entered at end of dtc data transfer) chain transfer every time chain transfer only when transfer counter = 0 sar?tc source address register h'bc00 to h'bfff dtc bit initial value read/write 23 * 22 * 21 * 20 * 19 * - - - - - - - - - - - - 4 * 3 * 2 * 1 * 0 * specifies data transfer source address * : undefined
461 dar?tc destination address register h'bc00 to h'bfff dtc bit initial value read/write 23 * 22 * 21 * 20 * 19 * 4 * 3 * 2 * 1 * 0 * specifies data transfer destination address * : undefined cra?tc transfer count register a h'bc00 to h'bfff dtc bit initial value read/write 15 * 14 * 13 * 12 * 11 * 10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1 * 0 * specifies number of dtc data transfers crah cral * : undefined crb?tc transfer count register b h'bc00 to h'bfff dtc * : undefined bit initial value read/write 15 * 14 * 13 * 12 * 11 * 10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1 * 0 * specifies number of dtc block data transfers
462 edsar0?xdma source address register 0 h'fdc0 exdmac * : undefined bit initial value read/write 15 * r/w 14 * r/w 13 * r/w 12 * r/w 11 * r/w 10 * r/w 9 * r/w 8 * r/w 7 * r/w 6 * r/w 5 * r/w 4 * r/w 3 * r/w 2 * r/w 1 * r/w 0 * r/w bit initial value read/write 31 0 30 0 29 0 28 0 27 0 26 0 25 0 24 0 23 * r/w 22 * r/w 21 * r/w 20 * r/w 19 * r/w 18 * r/w 17 * r/w 16 * r/w specifies transfer source address eddar0?xdma destination address register 0 h'fdc4 exdmac * : undefined bit initial value read/write 15 * r/w 14 * r/w 13 * r/w 12 * r/w 11 * r/w 10 * r/w 9 * r/w 8 * r/w 7 * r/w 6 * r/w 5 * r/w 4 * r/w 3 * r/w 2 * r/w 1 * r/w 0 * r/w bit initial value read/write 31 0 30 0 29 0 28 0 27 0 26 0 25 0 24 0 23 * r/w 22 * r/w 21 * r/w 20 * r/w 19 * r/w 18 * r/w 17 * r/w 16 * r/w specifies transfer destination address
463 edtcr0?xdma transfer count register 0 h'fdc8 exdmac * : undefined bit initial value read/write 15 * r/w 14 * r/w 13 * r/w 12 * r/w 11 * r/w 10 * r/w 9 * r/w 8 * r/w 7 * r/w 6 * r/w 5 * r/w 4 * r/w 3 * r/w 2 * r/w 1 * r/w 0 * r/w bit initial value read/write 31 0 30 0 29 0 28 0 27 0 26 0 25 0 24 0 23 * r/w 22 * r/w 21 * r/w 20 * r/w 19 * r/w 18 * r/w 17 * r/w 16 * r/w normal transfer mode: 24-bit transfer counter block transfer mode: block size (bits 23 to 16) 16-bit transfer counter (bits 15 to 0)
464 edmdr0?xdma mode control register 0 h'fdcc exdmac bit initial value read/write 15 eda 0 r/(w) * 1 14 bef 0 r/(w) * 2 13 edrake 0 r/w 12 etende 0 r/w 11 edreqs 0 r/w 10 ams 0 r/w 9 mds1 0 r/w 8 mds0 0 r/w address mode select 0 dual address mode 1 single address mode edreq select 0 low level sensing 1 falling edge sensing etend pin output enable 0 etend pin output disabled 1 etend pin output enabled edrak pin output enable 0 edrak pin output disabled 1 edrak pin output enabled block transfer error flag 0 no block transfer error [clearing condition] writing 0 to bef after reading bef = 1 1 block transfer error [setting condition] nmi interrupt during block transfer exdma active 0 data transfer disabled on corresponding channel [clearing conditions] when the specified number of transfers end when operation is halted by a repeat area overflow interrupt when 0 is written to eda while eda = 1 (in block transfer mode, write is effective after end of one-block transfer) reset, nmi interrupt, or hardware standby mode 1 data transfer enabled on corresponding channel. exdma operation in progress mode select 1 and 0 0 auto request, cycle steal mode, normal transfer mode 1 0 1 0 1 auto request, burst mode, normal transfer mode external request, cycle steal mode, normal transfer mode external request, cycle steal mode, block transfer mode notes: 1. the value written in bit eda may not be effective immediately. 2. bit bef can only be written with 0 after being read as 1, to clear the flag.
465 bit initial value read/write 7 edie 0 r/(w) 6 irf 0 r/(w) * 5 tceie 0 r/w 4 sdir 0 r/w 3 dtsize 0 r/w 2 bgup 0 r/w 1 0 r/w 0 0 r/w bus give-up 0 bus is not released in burst mode or block transfer mode 1 in burst mode or block transfer mode, the bus is transferred if requested by an internal bus master data transmit size 0 byte-size (8-bit) specification 1 word-size (16-bit) specification single address direction 0 transfer direction: edsar external device with dack 1 transfer direction: external device with dack eddar transfer counter end interrupt enable 0 transfer end interrupt requests by transfer counter are disabled 1 transfer end interrupt requests by transfer counter are enabled exdma interrupt enable 0 interrupt request is not generated 1 interrupt request is generated interrupt request flag 0 no interrupt request source [clearing conditions] writing 1 to the eda bit in edmdr writing 0 to irf after reading irf = 1 1 interrupt request source occurrence [setting conditions] transfer end interrupt request generated by transfer counter source address repeat area overflow interrupt request destination address repeat area overflow interrupt request note: * bit irf can only be written with 0 after being read as 1, to clear the flag.
466 edacr0?xdma address control register 0 h'fdce exdmac bit initial value read/write 15 sat1 0 r/w 14 sat0 0 r/w 13 sarie 0 r/w 12 sara4 0 r/w 11 sara3 0 r/w 10 sara2 0 r/w 9 sara1 0 r/w 8 sara0 0 r/w source address repeat interrupt enable 0 source address repeat interrupt is not requested 1 when source address repeat area overflow occurs, the irf bit in edmdr is set to 1 and an interrupt is requested source address repeat area 0 0 0 0 1 : 0 1 1 1 1 * source address (edsar) is not designated as repeat area lower 1 bit of edsar (2-byte area) designated as repeat area lower 2 bits of edsar (4-byte area) designated as repeat area lower 3 bits of edsar (8-byte area) designated as repeat area lower 4 bits of edsar (16-byte area) designated as repeat area : (continues in the same way) lower 19 bits of edsar (512-kbyte area) designated as repeat area lower 20 bits of edsar (1-mbyte area) designated as repeat area lower 21 bits of edsar (2-mbyte area) designated as repeat area lower 22 bits of edsar (4-mbyte area) designated as repeat area lower 23 bits of edsar (8-mbyte area) designated as repeat area reserved (setting prohibited) * : don t care 0 0 1 1 0 : 1 0 0 1 1 * 0 0 0 0 0 : 0 0 0 0 0 1 0 0 0 0 0 : 1 1 1 1 1 1 0 1 0 1 0 : 1 0 1 0 1 * source address update mode 0 1 * 0 1 source address (edsar) is fixed source address is incremented (+1 in byte transfer, +2 in word transfer) source address is decremented ( 1 in byte transfer, 2 in word transfer) * : don t care
467 bit initial value read/write 7 dat1 0 r/w 6 dat0 0 r/w 5 darie 0 r/w 4 dara4 0 r/w 3 dara3 0 r/w 2 dara2 0 r/w 1 dara1 0 r/w 0 dara0 0 r/w destination address repeat interrupt enable 0 destination address repeat interrupt is not requested 1 when destination address repeat area overflow occurs, the irf bit in edmdr is set to 1 and an interrupt is requested destination address repeat area 0 0 0 0 1 : 0 1 1 1 1 * destination address (eddar) is not designated as repeat area lower 1 bit of eddar (2-byte area) designated as repeat area lower 2 bits of eddar (4-byte area) designated as repeat area lower 3 bits of eddar (8-byte area) designated as repeat area lower 4 bits of eddar (16-byte area) designated as repeat area : (continues in the same way) lower 19 bits of eddar (512-kbyte area) designated as repeat area lower 20 bits of eddar (1-mbyte area) designated as repeat area lower 21 bits of eddar (2-mbyte area) designated as repeat area lower 22 bits of eddar (4-mbyte area) designated as repeat area lower 23 bits of eddar (8-mbyte area) designated as repeat area reserved (setting prohibited) * : don t care 0 0 1 1 0 : 1 0 0 1 1 * 0 0 0 0 0 : 0 0 0 0 0 1 0 0 0 0 0 : 1 1 1 1 1 1 0 1 0 1 0 : 1 0 1 0 1 * destination address update mode 0 1 * 0 1 destination address (eddar) is fixed destination address is incremented (+1 in byte transfer, +2 in word transfer) destination address is decremented ( 1 in byte transfer, 2 in word transfer) * : don t care
468 edsar1?xdma source address register 1 h'fdd0 exdmac * : undefined bit initial value read/write 15 * r/w 14 * r/w 13 * r/w 12 * r/w 11 * r/w 10 * r/w 9 * r/w 8 * r/w 7 * r/w 6 * r/w 5 * r/w 4 * r/w 3 * r/w 2 * r/w 1 * r/w 0 * r/w bit initial value read/write 31 0 30 0 29 0 28 0 27 0 26 0 25 0 24 0 23 * r/w 22 * r/w 21 * r/w 20 * r/w 19 * r/w 18 * r/w 17 * r/w 16 * r/w specifies transfer source address eddar1?xdma destination address register 1 h'fdd4 exdmac * : undefined bit initial value read/write 15 * r/w 14 * r/w 13 * r/w 12 * r/w 11 * r/w 10 * r/w 9 * r/w 8 * r/w 7 * r/w 6 * r/w 5 * r/w 4 * r/w 3 * r/w 2 * r/w 1 * r/w 0 * r/w bit initial value read/write 31 0 30 0 29 0 28 0 27 0 26 0 25 0 24 0 23 * r/w 22 * r/w 21 * r/w 20 * r/w 19 * r/w 18 * r/w 17 * r/w 16 * r/w specifies transfer destination address
469 edtcr1?xdma transfer count register 1 h'fdd8 exdmac * : undefined bit initial value read/write 15 * r/w 14 * r/w 13 * r/w 12 * r/w 11 * r/w 10 * r/w 9 * r/w 8 * r/w 7 * r/w 6 * r/w 5 * r/w 4 * r/w 3 * r/w 2 * r/w 1 * r/w 0 * r/w bit initial value read/write 31 0 30 0 29 0 28 0 27 0 26 0 25 0 24 0 23 * r/w 22 * r/w 21 * r/w 20 * r/w 19 * r/w 18 * r/w 17 * r/w 16 * r/w normal transfer mode: 24-bit transfer counter block transfer mode: block size (bits 23 to 16) 16-bit transfer counter (bits 15 to 0)
470 edmdr1?xdma mode control register 1 h'fddc exdmac bit initial value read/write 15 eda 0 r/(w) * 1 14 bef 0 r/(w) * 2 13 edrake 0 r/w 12 etende 0 r/w 11 edreqs 0 r/w 10 ams 0 r/w 9 mds1 0 r/w 8 mds0 0 r/w address mode select 0 dual address mode 1 single address mode edreq select 0 low level sensing 1 falling edge sensing etend pin output enable 0 etend pin output disabled 1 etend pin output enabled edrak pin output enable 0 edrak pin output disabled 1 edrak pin output enabled block transfer error flag 0 no block transfer error [clearing condition] writing 0 to bef after reading bef = 1 1 block transfer error [setting condition] nmi interrupt during block transfer exdma active 0 data transfer disabled on corresponding channel [clearing conditions] when the specified number of transfers end when operation is halted by a repeat area overflow interrupt when 0 is written to eda while eda = 1 (in block transfer mode, write is effective after end of one-block transfer) reset, nmi interrupt, or hardware standby mode 1 data transfer enabled on corresponding channel. exdma operation in progress mode select 1 and 0 0 auto request, cycle steal mode, normal transfer mode 1 0 1 0 1 auto request, burst mode, normal transfer mode external request, cycle steal mode, normal transfer mode external request, cycle steal mode, block transfer mode notes: 1. the value written in bit eda may not be effective immediately. 2. bit bef can only be written with 0 after being read as 1, to clear the flag.
471 bit initial value read/write 7 edie 0 r/(w) 6 irf 0 r/(w) * 5 tceie 0 r/w 4 sdir 0 r/w 3 dtsize 0 r/w 2 bgup 0 r/w 1 0 r/w 0 0 r/w bus give-up 0 bus is not released in burst mode or block transfer mode 1 in burst mode or block transfer mode, the bus is transferred if requested by an internal bus master data transmit size 0 byte-size (8-bit) specification 1 word-size (16-bit) specification single address direction 0 transfer direction: edsar external device with dack 1 transfer direction: external device with dack eddar transfer counter end interrupt enable 0 transfer end interrupt requests by transfer counter are disabled 1 transfer end interrupt requests by transfer counter are enabled exdma interrupt enable 0 interrupt request is not generated 1 interrupt request is generated interrupt request flag 0 no interrupt request source [clearing conditions] writing 1 to the eda bit in edmdr writing 0 to irf after reading irf = 1 1 interrupt request source occurrence [setting conditions] transfer end interrupt request generated by transfer counter source address repeat area overflow interrupt request destination address repeat area overflow interrupt request note: * bit irf can only be written with 0 after being read as 1, to clear the flag.
472 edacr1?xdma address control register 1 h'fdde exdmac bit initial value read/write 15 sat1 0 r/w 14 sat0 0 r/w 13 sarie 0 r/w 12 sara4 0 r/w 11 sara3 0 r/w 10 sara2 0 r/w 9 sara1 0 r/w 8 sara0 0 r/w source address repeat interrupt enable 0 source address repeat interrupt is not requested 1 when source address repeat area overflow occurs, the irf bit in edmdr is set to 1 and an interrupt is requested source address repeat area 0 0 0 0 1 : 0 1 1 1 1 * source address (edsar) is not designated as repeat area lower 1 bit of edsar (2-byte area) designated as repeat area lower 2 bits of edsar (4-byte area) designated as repeat area lower 3 bits of edsar (8-byte area) designated as repeat area lower 4 bits of edsar (16-byte area) designated as repeat area : (continues in the same way) lower 19 bits of edsar (512-kbyte area) designated as repeat area lower 20 bits of edsar (1-mbyte area) designated as repeat area lower 21 bits of edsar (2-mbyte area) designated as repeat area lower 22 bits of edsar (4-mbyte area) designated as repeat area lower 23 bits of edsar (8-mbyte area) designated as repeat area reserved (setting prohibited) * : don t care 0 0 1 1 0 : 1 0 0 1 1 * 0 0 0 0 0 : 0 0 0 0 0 1 0 0 0 0 0 : 1 1 1 1 1 1 0 1 0 1 0 : 1 0 1 0 1 * source address update mode 0 1 * 0 1 source address (edsar) is fixed source address is incremented (+1 in byte transfer, +2 in word transfer) source address is decremented ( 1 in byte transfer, 2 in word transfer) * : don t care
473 bit initial value read/write 7 dat1 0 r/w 6 dat0 0 r/w 5 darie 0 r/w 4 dara4 0 r/w 3 dara3 0 r/w 2 dara2 0 r/w 1 dara1 0 r/w 0 dara0 0 r/w destination address repeat interrupt enable 0 destination address repeat interrupt is not requested 1 when destination address repeat area overflow occurs, the irf bit in edmdr is set to 1 and an interrupt is requested destination address repeat area 0 0 0 0 1 : 0 1 1 1 1 * destination address (eddar) is not designated as repeat area lower 1 bit of eddar (2-byte area) designated as repeat area lower 2 bits of eddar (4-byte area) designated as repeat area lower 3 bits of eddar (8-byte area) designated as repeat area lower 4 bits of eddar (16-byte area) designated as repeat area : (continues in the same way) lower 19 bits of eddar (512-kbyte area) designated as repeat area lower 20 bits of eddar (1-mbyte area) designated as repeat area lower 21 bits of eddar (2-mbyte area) designated as repeat area lower 22 bits of eddar (4-mbyte area) designated as repeat area lower 23 bits of eddar (8-mbyte area) designated as repeat area reserved (setting prohibited) * : don t care 0 0 1 1 0 : 1 0 0 1 1 * 0 0 0 0 0 : 0 0 0 0 0 1 0 0 0 0 0 : 1 1 1 1 1 1 0 1 0 1 0 : 1 0 1 0 1 * destination address update mode 0 1 * 0 1 destination address (eddar) is fixed destination address is incremented (+1 in byte transfer, +2 in word transfer) destination address is decremented ( 1 in byte transfer, 2 in word transfer) * : don t care
474 edsar2?xdma source address register 2 h'fde0 exdmac * : undefined bit initial value read/write 15 * r/w 14 * r/w 13 * r/w 12 * r/w 11 * r/w 10 * r/w 9 * r/w 8 * r/w 7 * r/w 6 * r/w 5 * r/w 4 * r/w 3 * r/w 2 * r/w 1 * r/w 0 * r/w bit initial value read/write 31 0 30 0 29 0 28 0 27 0 26 0 25 0 24 0 23 * r/w 22 * r/w 21 * r/w 20 * r/w 19 * r/w 18 * r/w 17 * r/w 16 * r/w specifies transfer source address eddar2?xdma destination address register 2 h'fde4 exdmac * : undefined bit initial value read/write 15 * r/w 14 * r/w 13 * r/w 12 * r/w 11 * r/w 10 * r/w 9 * r/w 8 * r/w 7 * r/w 6 * r/w 5 * r/w 4 * r/w 3 * r/w 2 * r/w 1 * r/w 0 * r/w bit initial value read/write 31 0 30 0 29 0 28 0 27 0 26 0 25 0 24 0 23 * r/w 22 * r/w 21 * r/w 20 * r/w 19 * r/w 18 * r/w 17 * r/w 16 * r/w specifies transfer destination address
475 edtcr2?xdma transfer count register 2 h'fde8 exdmac * : undefined bit initial value read/write 15 * r/w 14 * r/w 13 * r/w 12 * r/w 11 * r/w 10 * r/w 9 * r/w 8 * r/w 7 * r/w 6 * r/w 5 * r/w 4 * r/w 3 * r/w 2 * r/w 1 * r/w 0 * r/w bit initial value read/write 31 0 30 0 29 0 28 0 27 0 26 0 25 0 24 0 23 * r/w 22 * r/w 21 * r/w 20 * r/w 19 * r/w 18 * r/w 17 * r/w 16 * r/w normal transfer mode: 24-bit transfer counter block transfer mode: block size (bits 23 to 16) 16-bit transfer counter (bits 15 to 0)
476 edmdr2?xdma mode control register 2 h'fdec exdmac bit initial value read/write 15 eda 0 r/(w) * 1 14 bef 0 r/(w) * 2 13 edrake 0 r/w 12 etende 0 r/w 11 edreqs 0 r/w 10 ams 0 r/w 9 mds1 0 r/w 8 mds0 0 r/w address mode select 0 dual address mode 1 single address mode edreq select 0 low level sensing 1 falling edge sensing etend pin output enable 0 etend pin output disabled 1 etend pin output enabled edrak pin output enable 0 edrak pin output disabled 1 edrak pin output enabled block transfer error flag 0 no block transfer error [clearing condition] writing 0 to bef after reading bef = 1 1 block transfer error [setting condition] nmi interrupt during block transfer exdma active 0 data transfer disabled on corresponding channel [clearing conditions] when the specified number of transfers end when operation is halted by a repeat area overflow interrupt when 0 is written to eda while eda = 1 (in block transfer mode, write is effective after end of one-block transfer) reset, nmi interrupt, or hardware standby mode 1 data transfer enabled on corresponding channel. exdma operation in progress mode select 1 and 0 0 auto request, cycle steal mode, normal transfer mode 1 0 1 0 1 auto request, burst mode, normal transfer mode external request, cycle steal mode, normal transfer mode external request, cycle steal mode, block transfer mode notes: 1. the value written in bit eda may not be effective immediately. 2. bit bef can only be written with 0 after being read as 1, to clear the flag.
477 bit initial value read/write 7 edie 0 r/(w) 6 irf 0 r/(w) * 5 tceie 0 r/w 4 sdir 0 r/w 3 dtsize 0 r/w 2 bgup 0 r/w 1 0 r/w 0 0 r/w bus give-up 0 bus is not released in burst mode or block transfer mode 1 in burst mode or block transfer mode, the bus is transferred if requested by an internal bus master data transmit size 0 byte-size (8-bit) specification 1 word-size (16-bit) specification single address direction 0 transfer direction: edsar external device with dack 1 transfer direction: external device with dack eddar transfer counter end interrupt enable 0 transfer end interrupt requests by transfer counter are disabled 1 transfer end interrupt requests by transfer counter are enabled exdma interrupt enable 0 interrupt request is not generated 1 interrupt request is generated interrupt request flag 0 no interrupt request source [clearing conditions] writing 1 to the eda bit in edmdr writing 0 to irf after reading irf = 1 1 interrupt request source occurrence [setting conditions] transfer end interrupt request generated by transfer counter source address repeat area overflow interrupt request destination address repeat area overflow interrupt request note: * bit irf can only be written with 0 after being read as 1, to clear the flag.
478 edacr2?xdma address control register 2 h'fdee exdmac bit initial value read/write 15 sat1 0 r/w 14 sat0 0 r/w 13 sarie 0 r/w 12 sara4 0 r/w 11 sara3 0 r/w 10 sara2 0 r/w 9 sara1 0 r/w 8 sara0 0 r/w source address repeat interrupt enable 0 source address repeat interrupt is not requested 1 when source address repeat area overflow occurs, the irf bit in edmdr is set to 1 and an interrupt is requested source address repeat area 0 0 0 0 1 : 0 1 1 1 1 * source address (edsar) is not designated as repeat area lower 1 bit of edsar (2-byte area) designated as repeat area lower 2 bits of edsar (4-byte area) designated as repeat area lower 3 bits of edsar (8-byte area) designated as repeat area lower 4 bits of edsar (16-byte area) designated as repeat area : (continues in the same way) lower 19 bits of edsar (512-kbyte area) designated as repeat area lower 20 bits of edsar (1-mbyte area) designated as repeat area lower 21 bits of edsar (2-mbyte area) designated as repeat area lower 22 bits of edsar (4-mbyte area) designated as repeat area lower 23 bits of edsar (8-mbyte area) designated as repeat area reserved (setting prohibited) * : don t care 0 0 1 1 0 : 1 0 0 1 1 * 0 0 0 0 0 : 0 0 0 0 0 1 0 0 0 0 0 : 1 1 1 1 1 1 0 1 0 1 0 : 1 0 1 0 1 * source address update mode 0 1 * 0 1 source address (edsar) is fixed source address is incremented (+1 in byte transfer, +2 in word transfer) source address is decremented ( 1 in byte transfer, 2 in word transfer) * : don t care
479 bit initial value read/write 7 dat1 0 r/w 6 dat0 0 r/w 5 darie 0 r/w 4 dara4 0 r/w 3 dara3 0 r/w 2 dara2 0 r/w 1 dara1 0 r/w 0 dara0 0 r/w destination address repeat interrupt enable 0 destination address repeat interrupt is not requested 1 when destination address repeat area overflow occurs, the irf bit in edmdr is set to 1 and an interrupt is requested destination address repeat area 0 0 0 0 1 : 0 1 1 1 1 * destination address (eddar) is not designated as repeat area lower 1 bit of eddar (2-byte area) designated as repeat area lower 2 bits of eddar (4-byte area) designated as repeat area lower 3 bits of eddar (8-byte area) designated as repeat area lower 4 bits of eddar (16-byte area) designated as repeat area : (continues in the same way) lower 19 bits of eddar (512-kbyte area) designated as repeat area lower 20 bits of eddar (1-mbyte area) designated as repeat area lower 21 bits of eddar (2-mbyte area) designated as repeat area lower 22 bits of eddar (4-mbyte area) designated as repeat area lower 23 bits of eddar (8-mbyte area) designated as repeat area reserved (setting prohibited) * : don t care 0 0 1 1 0 : 1 0 0 1 1 * 0 0 0 0 0 : 0 0 0 0 0 1 0 0 0 0 0 : 1 1 1 1 1 1 0 1 0 1 0 : 1 0 1 0 1 * destination address update mode 0 1 * 0 1 destination address (eddar) is fixed destination address is incremented (+1 in byte transfer, +2 in word transfer) destination address is decremented ( 1 in byte transfer, 2 in word transfer) * : don t care
480 edsar3?xdma source address register 3 h'fdf0 exdmac * : undefined bit initial value read/write 15 * r/w 14 * r/w 13 * r/w 12 * r/w 11 * r/w 10 * r/w 9 * r/w 8 * r/w 7 * r/w 6 * r/w 5 * r/w 4 * r/w 3 * r/w 2 * r/w 1 * r/w 0 * r/w bit initial value read/write 31 0 30 0 29 0 28 0 27 0 26 0 25 0 24 0 23 * r/w 22 * r/w 21 * r/w 20 * r/w 19 * r/w 18 * r/w 17 * r/w 16 * r/w specifies transfer source address eddar3?xdma destination address register 3 h'fdf4 exdmac * : undefined bit initial value read/write 15 * r/w 14 * r/w 13 * r/w 12 * r/w 11 * r/w 10 * r/w 9 * r/w 8 * r/w 7 * r/w 6 * r/w 5 * r/w 4 * r/w 3 * r/w 2 * r/w 1 * r/w 0 * r/w bit initial value read/write 31 0 30 0 29 0 28 0 27 0 26 0 25 0 24 0 23 * r/w 22 * r/w 21 * r/w 20 * r/w 19 * r/w 18 * r/w 17 * r/w 16 * r/w specifies transfer destination address
481 edtcr3?xdma transfer count register 3 h'fdf8 exdmac * : undefined bit initial value read/write 15 * r/w 14 * r/w 13 * r/w 12 * r/w 11 * r/w 10 * r/w 9 * r/w 8 * r/w 7 * r/w 6 * r/w 5 * r/w 4 * r/w 3 * r/w 2 * r/w 1 * r/w 0 * r/w bit initial value read/write 31 0 30 0 29 0 28 0 27 0 26 0 25 0 24 0 23 * r/w 22 * r/w 21 * r/w 20 * r/w 19 * r/w 18 * r/w 17 * r/w 16 * r/w normal transfer mode: 24-bit transfer counter block transfer mode: block size (bits 23 to 16) 16-bit transfer counter (bits 15 to 0)
482 edmdr3?xdma mode control register 3 h'fdfc exdmac bit initial value read/write 15 eda 0 r/(w) * 1 14 bef 0 r/(w) * 2 13 edrake 0 r/w 12 etende 0 r/w 11 edreqs 0 r/w 10 ams 0 r/w 9 mds1 0 r/w 8 mds0 0 r/w address mode select 0 dual address mode 1 single address mode edreq select 0 low level sensing 1 falling edge sensing etend pin output enable 0 etend pin output disabled 1 etend pin output enabled edrak pin output enable 0 edrak pin output disabled 1 edrak pin output enabled block transfer error flag 0 no block transfer error [clearing condition] writing 0 to bef after reading bef = 1 1 block transfer error [setting condition] nmi interrupt during block transfer exdma active 0 data transfer disabled on corresponding channel [clearing conditions] when the specified number of transfers end when operation is halted by a repeat area overflow interrupt when 0 is written to eda while eda = 1 (in block transfer mode, write is effective after end of one-block transfer) reset, nmi interrupt, or hardware standby mode 1 data transfer enabled on corresponding channel. exdma operation in progress mode select 1 and 0 0 auto request, cycle steal mode, normal transfer mode 1 0 1 0 1 auto request, burst mode, normal transfer mode external request, cycle steal mode, normal transfer mode external request, cycle steal mode, block transfer mode notes: 1. the value written in bit eda may not be effective immediately. 2. bit bef can only be written with 0 after being read as 1, to clear the flag.
483 bit initial value read/write 7 edie 0 r/(w) 6 irf 0 r/(w) * 5 tceie 0 r/w 4 sdir 0 r/w 3 dtsize 0 r/w 2 bgup 0 r/w 1 0 r/w 0 0 r/w bus give-up 0 bus is not released in burst mode or block transfer mode 1 in burst mode or block transfer mode, the bus is transferred if requested by an internal bus master data transmit size 0 byte-size (8-bit) specification 1 word-size (16-bit) specification single address direction 0 transfer direction: edsar external device with dack 1 transfer direction: external device with dack eddar transfer counter end interrupt enable 0 transfer end interrupt requests by transfer counter are disabled 1 transfer end interrupt requests by transfer counter are enabled exdma interrupt enable 0 interrupt request is not generated 1 interrupt request is generated interrupt request flag 0 no interrupt request source [clearing conditions] writing 1 to the eda bit in edmdr writing 0 to irf after reading irf = 1 1 interrupt request source occurrence [setting conditions] transfer end interrupt request generated by transfer counter source address repeat area overflow interrupt request destination address repeat area overflow interrupt request note: * bit irf can only be written with 0 after being read as 1, to clear the flag.
484 edacr3?xdma address control register 3 h'fdfe exdmac bit initial value read/write 15 sat1 0 r/w 14 sat0 0 r/w 13 sarie 0 r/w 12 sara4 0 r/w 11 sara3 0 r/w 10 sara2 0 r/w 9 sara1 0 r/w 8 sara0 0 r/w source address repeat interrupt enable 0 source address repeat interrupt is not requested 1 when source address repeat area overflow occurs, the irf bit in edmdr is set to 1 and an interrupt is requested source address repeat area 0 0 0 0 1 : 0 1 1 1 1 * source address (edsar) is not designated as repeat area lower 1 bit of edsar (2-byte area) designated as repeat area lower 2 bits of edsar (4-byte area) designated as repeat area lower 3 bits of edsar (8-byte area) designated as repeat area lower 4 bits of edsar (16-byte area) designated as repeat area : (continues in the same way) lower 19 bits of edsar (512-kbyte area) designated as repeat area lower 20 bits of edsar (1-mbyte area) designated as repeat area lower 21 bits of edsar (2-mbyte area) designated as repeat area lower 22 bits of edsar (4-mbyte area) designated as repeat area lower 23 bits of edsar (8-mbyte area) designated as repeat area reserved (setting prohibited) * : don t care 0 0 1 1 0 : 1 0 0 1 1 * 0 0 0 0 0 : 0 0 0 0 0 1 0 0 0 0 0 : 1 1 1 1 1 1 0 1 0 1 0 : 1 0 1 0 1 * source address update mode 0 1 * 0 1 source address (edsar) is fixed source address is incremented (+1 in byte transfer, +2 in word transfer) source address is decremented ( 1 in byte transfer, 2 in word transfer) * : don t care
485 bit initial value read/write 7 dat1 0 r/w 6 dat0 0 r/w 5 darie 0 r/w 4 dara4 0 r/w 3 dara3 0 r/w 2 dara2 0 r/w 1 dara1 0 r/w 0 dara0 0 r/w destination address repeat interrupt enable 0 destination address repeat interrupt is not requested 1 when destination address repeat area overflow occurs, the irf bit in edmdr is set to 1 and an interrupt is requested destination address repeat area 0 0 0 0 1 : 0 1 1 1 1 * destination address (eddar) is not designated as repeat area lower 1 bit of eddar (2-byte area) designated as repeat area lower 2 bits of eddar (4-byte area) designated as repeat area lower 3 bits of eddar (8-byte area) designated as repeat area lower 4 bits of eddar (16-byte area) designated as repeat area : (continues in the same way) lower 19 bits of eddar (512-kbyte area) designated as repeat area lower 20 bits of eddar (1-mbyte area) designated as repeat area lower 21 bits of eddar (2-mbyte area) designated as repeat area lower 22 bits of eddar (4-mbyte area) designated as repeat area lower 23 bits of eddar (8-mbyte area) designated as repeat area reserved (setting prohibited) * : don t care 0 0 1 1 0 : 1 0 0 1 1 * 0 0 0 0 0 : 0 0 0 0 0 1 0 0 0 0 0 : 1 1 1 1 1 1 0 1 0 1 0 : 1 0 1 0 1 * destination address update mode 0 1 * 0 1 destination address (eddar) is fixed destination address is incremented (+1 in byte transfer, +2 in word transfer) destination address is decremented ( 1 in byte transfer, 2 in word transfer) * : don t care
486 ipra?nterrupt priority register a h'fe00 interrupt controller iprb?nterrupt priority register b h'fe02 interrupt controller iprc?nterrupt priority register c h'fe04 interrupt controller iprd?nterrupt priority register d h'fe06 interrupt controller ipre?nterrupt priority register e h'fe08 interrupt controller iprf?nterrupt priority register f h'fe0a interrupt controller iprg?nterrupt priority register g h'fe0c interrupt controller iprh?nterrupt priority register h h'fe0e interrupt controller ipri?nterrupt priority register i h'fe10 interrupt controller iprj?nterrupt priority register j h'fe12 interrupt controller iprk?nterrupt priority register k h'fe14 interrupt controller bit initial value read/write 15 0 14 ipr14 1 r/w 13 ipr13 1 r/w 12 ipr12 1 r/w 11 0 10 ipr10 1 r/w 9 ipr9 1 r/w 8 ipr8 1 r/w bit initial value read/write 7 0 6 ipr6 1 r/w 5 ipr5 1 r/w 4 ipr4 1 r/w 3 0 2 ipr2 1 r/w 1 ipr1 1 r/w 0 ipr0 1 r/w interrupt sources and ipr settings interrupt priority settings bits 14 to 12 ipra iprb iprc iprd ipre iprf iprg iprh ipri iprj iprk irq0 irq4 irq8 irq12 dtc * tpu channel 2 8-bit timer channel 0 exdmac channel 1 sci channel 1 * register bits 10 to 8 irq1 irq5 irq9 irq13 interval timer a/d converter tpu channel 3 8-bit timer channel 1 exdmac channel 2 sci channel 2 * note: * reserved bits. these bits are always read as h'7 and should also be written with h'7. bits 6 to 4 irq2 irq6 irq10 irq14 * tpu channel 0 tpu channel 4 dmac exdmac channel 3 * * bits 2 to 0 irq3 irq7 irq11 irq15 refresh timer tpu channel 1 tpu channel 5 exdmac channel 0 sci channel 0 * *
487 itsr?rq pin select register h'fe16 interrupt controller bit initial value read/write 15 its15 0 r/w 14 its14 0 r/w 13 its13 0 r/w 12 its12 0 r/w 11 its11 0 r/w 10 its10 0 r/w 9 its9 0 r/w 8 its8 0 r/w bit initial value read/write 7 its7 0 r/w 6 its6 0 r/w 5 its5 0 r/w 4 its4 0 r/w 3 its3 0 r/w 2 its2 0 r/w 1 its1 0 r/w 0 its0 0 r/w irq input pin select 0 itsn irqn requests are accepted at the irqn pin description 1 irqn requests are accepted at the ( irqn ) pin (n = 15 to 0)
488 ssier?oftware standby release irq enable register h'fe18 interrupt controller bit initial value read/write 15 ssi15 0 r/w 14 ssi14 0 r/w 13 ssi13 0 r/w 12 ssi12 0 r/w 11 ssi11 0 r/w 10 ssi10 0 r/w 9 ssi9 0 r/w 8 ssi8 0 r/w bit initial value read/write 7 ssi7 0 r/w 6 ssi6 0 r/w 5 ssi5 0 r/w 4 ssi4 0 r/w 3 ssi3 0 r/w 2 ssi2 0 r/w 1 ssi1 0 r/w 0 ssi0 0 r/w software standby release irq setting 0 ssin irqn requests are not sampled in the software standby state description 1 when an irqn request occurs in the software standby state, the chip recovers from the software standby state after the elapse of the oscillation settling time (n = 15 to 0)
489 iscrh?rq sense control register h h'fe1a interrupt controller iscrl?rq sense control register l h'fe1c interrupt controller iscrl bit initial value read/write 15 irq7scb 0 r/w 14 irq7sca 0 r/w 13 irq6scb 0 r/w 12 irq6sca 0 r/w 11 irq5scb 0 r/w 10 irq5sca 0 r/w 9 irq4scb 0 r/w 8 irq4sca 0 r/w bit initial value read/write 7 irq3scb 0 r/w 6 irq3sca 0 r/w 5 irq2scb 0 r/w 4 irq2sca 0 r/w 3 irq1scb 0 r/w 2 irq1sca 0 r/w 1 irq0scb 0 r/w 0 irq0sca 0 r/w iscrh bit initial value read/write 15 irq15scb 0 r/w 14 irq15sca 0 r/w 13 irq14scb 0 r/w 12 irq14sca 0 r/w 11 irq13scb 0 r/w 10 irq13sca 0 r/w 9 irq12scb 0 r/w 8 irq12sca 0 r/w bit initial value read/write 7 irq11scb 0 r/w 6 irq11sca 0 r/w 5 irq10scb 0 r/w 4 irq10sca 0 r/w 3 irq9scb 0 r/w 2 irq9sca 0 r/w 1 irq8scb 0 r/w 0 irq8sca 0 r/w irq15 sense control a and b to irq0 sense control a and b 0 irqnsca interrupt request generated at irqn input low level description 1 interrupt request generated at falling edge of irqn input 0 irqnscb 0 interrupt request generated at rising edge of irqn input 1 1 interrupt request generated at both falling and rising edges of irqn input (n = 15 to 0)
490 ircr?rda control register h'fe1e irda bit initial value read/write 7 ire 0 r/w 6 ircks2 0 r/w 5 ircks1 0 r/w 4 ircks0 0 r/w 3 0 2 0 1 0 0 0 irda enable 0 pins txd0/irtxd and rxd0/irrxd function as txd0 and rxd0 1 pins txd0/irtxd and rxd0/irrxd function as irtxd and irrxd irda clock select 2 to 0 0b 3/16 (3/16 of bit rate) 1 0 1 /2 /4 /8 /16 /32 0 1 0 1 00 1 /64 10 /128 1 p1ddr?ort 1 data direction register h'fe20 port 1 bit initial value read/write 7 p17ddr 0 w 6 p16ddr 0 w 5 p15ddr 0 w 4 p14ddr 0 w 3 p13ddr 0 w 2 p12ddr 0 w 1 p11ddr 0 w 0 p10ddr 0 w specify input or output for individual port 1 pins
491 p2ddr?ort 2 data direction register h'fe21 port 2 bit initial value read/write 7 p27ddr 0 w 6 p26ddr 0 w 5 p25ddr 0 w 4 p24ddr 0 w 3 p23ddr 0 w 2 p22ddr 0 w 1 p21ddr 0 w 0 p20ddr 0 w specify input or output for individual port 2 pins p3ddr?ort 3 data direction register h'fe22 port 3 bit initial value read/write 7 0 6 0 5 p35ddr 0 w 4 p34ddr 0 w 3 p33ddr 0 w 2 p32ddr 0 w 1 p31ddr 0 w 0 p30ddr 0 w specify input or output for individual port 3 pins p5ddr?ort 5 data direction register h'fe24 port 5 bit initial value read/write 7 0 6 0 5 0 4 0 3 p53ddr 0 w 2 p52ddr 0 w 1 p51ddr 0 w 0 p50ddr 0 w specify input or output for individual port 5 pins p6ddr?ort 6 data direction register h'fe25 port 6 bit initial value read/write 7 0 6 0 5 p65ddr 0 w 4 p64ddr 0 w 3 p63ddr 0 w 2 p62ddr 0 w 1 p61ddr 0 w 0 p60ddr 0 w specify input or output for individual port 6 pins
492 p7ddr?ort 7 data direction register h'fe26 port 7 bit initial value read/write 7 0 6 0 5 p75ddr 0 w 4 p74ddr 0 w 3 p73ddr 0 w 2 p72ddr 0 w 1 p71ddr 0 w 0 p70ddr 0 w specify input or output for individual port 7 pins p8ddr?ort 8 data direction register h'fe27 port 8 bit initial value read/write 7 0 6 0 5 p85ddr 0 w 4 p84ddr 0 w 3 p83ddr 0 w 2 p82ddr 0 w 1 p81ddr 0 w 0 p80ddr 0 w specify input or output for individual port 8 pins paddr?ort a data direction register h'fe29 port a bit initial value read/write 7 pa7ddr 0 w 6 pa6ddr 0 w 5 pa5ddr 0 w 4 pa4ddr 0 w 3 pa3ddr 0 w 2 pa2ddr 0 w 1 pa1ddr 0 w 0 pa0ddr 0 w specify input or output for individual port a pins pbddr?ort b data direction register h'fe2a port b bit initial value read/write 7 pb7ddr 0 w 6 pb6ddr 0 w 5 pb5ddr 0 w 4 pb4ddr 0 w 3 pb3ddr 0 w 2 pb2ddr 0 w 1 pb1ddr 0 w 0 pb0ddr 0 w specify input or output for individual port b pins
493 pcddr?ort c data direction register h'fe2b port c bit initial value read/write 7 pc7ddr 0 w 6 pc6ddr 0 w 5 pc5ddr 0 w 4 pc4ddr 0 w 3 pc3ddr 0 w 2 pc2ddr 0 w 1 pc1ddr 0 w 0 pc0ddr 0 w specify input or output for individual port c pins pdddr?ort d data direction register h'fe2c port d bit initial value read/write 7 pd7ddr 0 w 6 pd6ddr 0 w 5 pd5ddr 0 w 4 pd4ddr 0 w 3 pd3ddr 0 w 2 pd2ddr 0 w 1 pd1ddr 0 w 0 pd0ddr 0 w specify input or output for individual port d pins peddr?ort e data direction register h'fe2d port e bit initial value read/write 7 pe7ddr 0 w 6 pe6ddr 0 w 5 pe5ddr 0 w 4 pe4ddr 0 w 3 pe3ddr 0 w 2 pe2ddr 0 w 1 pe1ddr 0 w 0 pe0ddr 0 w specify input or output for individual port e pins
494 pfddr?ort f data direction register h'fe2e port f bit modes 1, 2, 4, 5, 6 initial value read/write mode 7 initial value read/write 7 pf7ddr 1 w 0 w 6 pf6ddr 0 w 0 w 5 pf5ddr 0 w 0 w 4 pf4ddr 0 w 0 w 3 pf3ddr 0 w 0 w 2 pf2ddr 0 w 0 w 1 pf1ddr 0 w 0 w 0 pf0ddr 0 w 0 w specify input or output for individual port f pins pgddr?ort g data direction register h'fe2f port g bit modes 1, 2, 5, 6 initial value read/write modes 4, 7 initial value read/write 7 0 w 0 w 6 pg6ddr 0 w 0 w 5 pg5ddr 0 w 0 w 4 pg4ddr 0 w 0 w 3 pg3ddr 0 w 0 w 2 pg2ddr 0 w 0 w 1 pg1ddr 0 w 0 w 0 pg0ddr 0 w 0 w specify input or output for individual port g pins
495 pfcr0?ort function control register 0 h'fe32 ports bit initial value read/write 7 cs7e 1 r/w 6 cs6e 1 r/w 5 cs5e 1 r/w 4 cs4e 1 r/w 3 cs3e 1 r/w 2 cs2e 1 r/w 1 cs1e 1 r/w 0 cs0e 1 r/w cs7 to cs0 enable (n = 7 to 0) 0 pin is designated as i/o port and does not function as csn output pin 1 pin is designated as csn output pin pfcr1?ort function control register 1 h'fe33 ports bit initial value read/write 7 a23e 1 r/w 6 a22e 1 r/w 5 a21e 1 r/w 4 a20e 1 r/w 3 a19e 1 r/w 2 a18e 1 r/w 1 a17e 1 r/w 0 a16e 1 r/w address 23 to 16 enable (n = 7 to 0, m = 23 to 16) 0 dr output when panddr = 1 1 am output when panddr = 1
496 pfcr2?ort function control register 2 h'fe34 ports bit initial value read/write 7 0 6 0 5 0 4 0 3 asoe 1 r/w 2 lwroe 1 r/w 1 oes 1 r/w 0 dmacs 1 r/w dmac control pin select 0 p65 to p60 are designated as dmac control pins 1 p75 to p70 are designated as dmac control pins oe output select 0 p35 is designated as oe output pin 1 ph3 is designated as oe output pin lwr output enable 0 pf6 is designated as i/o port and does not function as lwr output pin 1 pf6 is designated as lwr output pin as output enable 0 pf6 is designated as i/o port and does not function as as output pin 1 pf6 is designated as as output pin
497 papcr?ort a mos pull-up control register h'fe36 port a bit initial value read/write 7 pa7pcr 0 r/w 6 pa6pcr 0 r/w 5 pa5pcr 0 r/w 4 pa4pcr 0 r/w 3 pa3pcr 0 r/w 2 pa2pcr 0 r/w 1 pa1pcr 0 r/w 0 pa0pcr 0 r/w bit-by-bit control of mos input pull-up function incorporated into port a pbpcr?ort b mos pull-up control register h'fe37 port b bit initial value read/write 7 pb7pcr 0 r/w 6 pb6pcr 0 r/w 5 pb5pcr 0 r/w 4 pb4pcr 0 r/w 3 pb3pcr 0 r/w 2 pb2pcr 0 r/w 1 pb1pcr 0 r/w 0 pb0pcr 0 r/w bit-by-bit control of mos input pull-up function incorporated into port b pcpcr?ort c mos pull-up control register h'fe38 port c bit initial value read/write 7 pc7pcr 0 r/w 6 pc6pcr 0 r/w 5 pc5pcr 0 r/w 4 pc4pcr 0 r/w 3 pc3pcr 0 r/w 2 pc2pcr 0 r/w 1 pc1pcr 0 r/w 0 pc0pcr 0 r/w bit-by-bit control of mos input pull-up function incorporated into port c pdpcr?ort d mos pull-up control register h'fe39 port d bit initial value read/write 7 pd7pcr 0 r/w 6 pd6pcr 0 r/w 5 pd5pcr 0 r/w 4 pd4pcr 0 r/w 3 pd3pcr 0 r/w 2 pd2pcr 0 r/w 1 pd1pcr 0 r/w 0 pd0pcr 0 r/w bit-by-bit control of mos input pull-up function incorporated into port d
498 pepcr?ort e mos pull-up control register h'fe3a port e bit initial value read/write 7 pe7pcr 0 r/w 6 pe6pcr 0 r/w 5 pe5pcr 0 r/w 4 pe4pcr 0 r/w 3 pe3pcr 0 r/w 2 pe2pcr 0 r/w 1 pe1pcr 0 r/w 0 pe0pcr 0 r/w bit-by-bit control of mos input pull-up function incorporated into port e p3odr?ort 3 open drain control register h'fe3c port 3 bit initial value read/write 7 0 6 0 5 p35odr 0 r/w 4 p34odr 0 r/w 3 p33odr 0 r/w 2 p32odr 0 r/w 1 p31odr 0 r/w 0 p30odr 0 r/w control pmos on/off status for each port 3 pin (p35 to p30) paodr?ort a open drain control register h'fe3d port a bit initial value read/write 7 pa7odr 0 r/w 6 pa6odr 0 r/w 5 pa5odr 0 r/w 4 pa4odr 0 r/w 3 pa3odr 0 r/w 2 pa2odr 0 r/w 1 pa1odr 0 r/w 0 pa0odr 0 r/w control pmos on/off status for each port a pin (pa7 to pa0)
499 tcr3?imer control register 3 h'fe80 tpu3 bit initial value read/write 7 cclr2 0 r/w 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w 0 tpsc0 0 r/w 0 1 0 1 0 1 internal clock: count on /1 internal clock: count on /4 internal clock: count on /16 internal clock: count on /64 external clock: count on tclka pin input internal clock: count on /1024 internal clock: count on /256 internal clock: count on /4096 timer prescaler 0 1 0 1 0 1 0 1 0 1 0 1 count at rising edge count at falling edge count at both edges clock edge 0 0 tcnt clearing disabled tcnt cleared by tgra compare match/input capture tcnt cleared by tgrb compare match/input capture counter clear 0 1 10 1 100 1 10 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * 1 tcnt clearing disabled tcnt cleared by tgrc compare match/input capture * 2 tcnt cleared by tgrd compare match/input capture * 2 tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * 1 notes: 1. synchronous operation is selected by setting the sync bit in tsyr to 1. 2. when tgrc or tgrd is used as a buffer register, tcnt is not cleared because the buffer register setting has priority, and compare match/input capture does not occur.
500 tmdr3?imer mode register 3 h'fe81 tpu3 bit initial value read/write 7 1 6 1 5 bfb 0 r/w 4 bfa 0 r/w 3 md3 0 r/w 2 md2 0 r/w 1 md1 0 r/w 0 md0 0 r/w 0 0 normal operation reserved pwm mode 1 pwm mode 2 phase counting mode 1 phase counting mode 2 phase counting mode 3 phase counting mode 4 mode 1 1 * 0 1 0 1 * 0 1 0 1 0 1 0 1 * * : don t care notes: 1. md3 is a reserved bit. in a write, it should always be written with 0. 2. phase counting mode cannot be set for channels 0 and 3. in this case, 0 should always be written to md2. 0 tgra operates normally tgra and tgrc used together for buffer operation tgra buffer operation 1 0 tgrb operates normally tgrb and tgrd used together for buffer operation tgrb buffer operation 1
501 tior3h?imer i/o control register 3h h'fe82 tpu3 bit initial value read/write 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w 0 ioa0 0 r/w 0 0 tgr3a i/o control 0 0 1 tgr3a is output compare register 10 1 100 1 10 1 0 1 0 0 tgr3a is input capture register 1 1 * output disabled initial output is 1 output output disabled initial output is 0 output capture input source is tioca3 pin 0 output at compare match 1 output at compare match toggle output at compare match * : don t care 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges ** 1 capture input source is channel 4/count clock input capture at tcnt4 count-up/ count-down 0 0 tgr3b i/o control 0 0 1 tgr3b is output compare register 10 1 100 1 10 1 0 1 0 0 tgr3b is input capture register 1 1 * output disabled initial output is 1 output output disabled initial output is 0 output capture input source is tiocb3 pin 0 output at compare match 1 output at compare match toggle output at compare match * : don t care 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges ** 1 capture input source is channel 4/count clock input capture at tcnt4 count-up/ count-down * 1 note: 1. when bits tpsc2 to tpsc0 in tcr4 are set to b 000 and /1 is used as the tcnt4 count clock, this setting is invalid and input capture does not occur.
502 tior3l?imer i/o control register 3l h'fe83 tpu3 bit initial value read/write 7 iod3 0 r/w 6 iod2 0 r/w 5 iod1 0 r/w 4 iod0 0 r/w 3 ioc3 0 r/w 2 ioc2 0 r/w 1 ioc1 0 r/w 0 ioc0 0 r/w 0 0 trg3c i/o control 0 0 1 tgr3c is output compare register 10 1 100 1 10 1 0 1 0 0 tgr3c is input capture register 1 1 * output disabled initial output is 1 output output disabled initial output is 0 output capture input source is tiocc3 pin 0 output at compare match 1 output at compare match toggle output at compare match * : don t care 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges ** 1 capture input source is channel 4/count clock input capture at tcnt4 count-up/ count-down 0 0 tgr3d i/o control 0 0 1 tgr3d is output compare register * 2 10 1 100 1 10 1 0 1 0 0 tgr3d is input capture register * 2 1 1 * output disabled initial output is 1 output output disabled initial output is 0 output capture input source is tiocd3 pin 0 output at compare match 1 output at compare match toggle output at compare match * : don t care 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges ** 1 capture input source is channel 4/count clock input capture at tcnt4 count-up/ count-down * 1 note: when the bfa bit in tmdr3 is set to 1 and tgr3c is used as a buffer register, this setting is invalid and input capture/output compare does not occur. notes: 1. when bits tpsc2 to tpsc0 in tcr4 are set to b 000 and /1 is used as the tcnt4 count clock, this setting is invalid and input capture does not occur. 2. when the bfb bit in tmdr3 is set to 1 and tgr3d is used as a buffer register, this setting is invalid and input capture/output compare does not occur. note: when tgrc or tgrd is designated for buffer operation, these settings are invalid and the register operates as a buffer register.
503 tier3?imer interrupt enable register 3 h'fe84 tpu3 bit initial value read/write 7 ttge 0 r/w 6 1 5 0 4 tciev 0 r/w 3 tgied 0 r/w 2 tgiec 0 r/w 1 tgieb 0 r/w 0 tgiea 0 r/w 0 tgr interrupt enable a 1 0 tgr interrupt enable b 1 0 tgr interrupt enable c 1 0 tgr interrupt enable d 1 0 interrupt request (tciv) by tcfv disabled interrupt request (tciv) by tcfv enabled overflow interrupt enable 1 0 a/d conversion start request generation disabled a/d conversion start request generation enabled a/d conversion start request enable 1 interrupt request (tgia) by tgfa bit disabled interrupt request (tgia) by tgfa bit enabled interrupt request (tgib) by tgfb bit disabled interrupt request (tgib) by tgfb bit enabled interrupt request (tgic) by tgfc bit disabled interrupt request (tgic) by tgfc bit enabled interrupt request (tgid) by tgfd bit disabled interrupt request (tgid) by tgfd bit enabled
504 tsr3?imer status register 3 h'fe85 tpu3 bit initial value read/write 7 1 6 1 5 0 4 tcfv 0 r/(w) * 3 tgfd 0 r/(w) * 2 tgfc 0 r/(w) * 1 tgfb 0 r/(w) * 0 tgfa 0 r/(w) * 0 input capture/output compare flag a 1 0 input capture/output compare flag b 1 0 input capture/output compare flag c 1 note: * can only be written with 0, to clear the flag. 0 input capture/output compare flag d 1 0 [clearing condition] when 0 is written to tcfv after reading tcfv = 1 [setting condition] when the tcnt value overflows (from h'ffff to h'0000) overflow flag 1 [clearing conditions] when dtc is activated by tgia interrupt and disel bit in dtc s mrb register is 0 when dmac is activated by tgia interrupt and dta bit in dmac s dmabcr register is 1 when 0 is written to tgfa after reading tgfa = 1 [clearing conditions] when dtc is activated by tgib interrupt and disel bit in dtc s mrb register is 0 when 0 is written to tgfb after reading tgfb = 1 [setting conditions] when tcnt = tgrb while tgrb is functioning as output compare register when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register [clearing conditions] when dtc is activated by tgic interrupt and disel bit in dtc s mrb register is 0 when 0 is written to tgfc after reading tgfc = 1 [setting conditions] when tcnt = tgrc while tgrc is functioning as output compare register when tcnt value is transferred to tgrc by input capture signal while tgrc is functioning as input capture register [clearing conditions] when dtc is activated by tgid interrupt and disel bit in dtc s mrb register is 0 when 0 is written to tgfd after reading tgfd = 1 [setting conditions] when tcnt = tgrd while tgrd is functioning as output compare register when tcnt value is transferred to tgrd by input capture signal while tgrd is functioning as input capture register [setting conditions] when tcnt = tgra while tgra is functioning as output compare register when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register
505 tcnt3?imer counter 3 h'fe86 tpu3 bit initial value read/write 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 10 0 r/w 9 0 r/w 8 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w up-counter tgr3a?imer general register 3a h'fe88 tpu3 tgr3b?imer general register 3b h'fe8a tpu3 tgr3c?imer general register 3c h'fe8c tpu3 tgr3d?imer general register 3d h'fe8e tpu3 bit initial value read/write 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w
506 tcr4?imer control register 4 h'fe90 tpu4 bit initial value read/write 7 0 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w 0 tpsc0 0 r/w 0 1 0 1 0 1 internal clock: count on /1 internal clock: count on /4 internal clock: count on /16 internal clock: count on /64 external clock: count on tclka pin input external clock: count on tclkc pin input internal clock: count on /1024 count on tcnt5 overflow/underflow timer prescaler 0 1 0 1 0 1 0 1 0 1 0 1 count at rising edge count at falling edge count at both edges clock edge 0 tcnt clearing disabled tcnt cleared by tgra compare match/input capture tcnt cleared by tgrb compare match/input capture counter clear 0 1 10 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * note: this setting is invalid when channel 4 is in phase counting mode. note: this setting is invalid when channel 4 is in phase counting mode. note: * synchronous operation is selected by setting the sync bit in tsyr to 1.
507 tmdr4?imer mode register 4 h'fe91 tpu4 bit initial value read/write 7 1 6 1 5 0 4 0 3 md3 0 r/w 2 md2 0 r/w 1 md1 0 r/w 0 md0 0 r/w 0 0 normal operation reserved pwm mode 1 pwm mode 2 phase counting mode 1 phase counting mode 2 phase counting mode 3 phase counting mode 4 mode 1 1 * 0 1 0 1 * 0 1 0 1 0 1 0 1 * * : don t care note: md3 is a reserved bit. in a write, it should always be written with 0.
508 tior4?imer i/o control register 4 h'fe92 tpu4 bit initial value read/write 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w 0 ioa0 0 r/w 0 0 tgr4a i/o control 0 0 1 tgr4a is output compare register 10 1 100 1 10 1 0 1 0 0 tgr4a is input capture register 1 1 * output disabled initial output is 1 output output disabled initial output is 0 output capture input source is tioca4 pin 0 output at compare match 1 output at compare match toggle output at compare match * : don t care 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges ** 1 capture input source is tgr3a compare match/ input capture input capture at generation of tgr3a compare match/input capture 0 0 tgr4b i/o control 0 0 1 tgr4b is output compare register 10 1 100 1 10 1 0 1 0 0 tgr4b is input capture register 1 1 * output disabled initial output is 1 output output disabled initial output is 0 output capture input source is tiocb4 pin 0 output at compare match 1 output at compare match toggle output at compare match * : don t care 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges ** 1 capture input source is tgr3c compare match/ input capture input capture at generation of tgr3c compare match/input capture
509 tier4?imer interrupt enable register 4 h'fe94 tpu4 bit initial value read/write 7 ttge 0 r/w 6 1 5 tcieu 0 r/w 4 tciev 0 r/w 3 0 2 0 1 tgieb 0 r/w 0 tgiea 0 r/w 0 tgr interrupt enable a 1 0 tgr interrupt enable b 1 0 interrupt request (tciv) by tcfv disabled interrupt request (tciv) by tcfv enabled overflow interrupt enable 1 0 a/d conversion start request generation disabled a/d conversion start request generation enabled a/d conversion start request enable 1 0 interrupt request (tciu) by tcfu disabled interrupt request (tciu) by tcfu enabled underflow interrupt enable 1 interrupt request (tgia) by tgfa bit disabled interrupt request (tgia) by tgfa bit enabled interrupt request (tgib) by tgfb bit disabled interrupt request (tgib) by tgfb bit enabled
510 tsr4?imer status register 4 h'fe95 tpu4 bit initial value read/write 7 tcfd 1 r 6 1 5 tcfu 0 r/(w) * 4 tcfv 0 r/(w) * 3 0 2 0 1 tgfb 0 r/(w) * 0 tgfa 0 r/(w) * 0 input capture/output compare flag a 1 0 input capture/output compare flag b 1 0 [clearing condition] when 0 is written to tcfv after reading tcfv = 1 [setting condition] when the tcnt value overflows (from h'ffff to h'0000) overflow flag 1 0 [clearing condition] when 0 is written to tcfu after reading tcfu = 1 [setting condition] when the tcnt value underflows (from h'0000 to h'ffff) underflow flag 1 0 tcnt counts down tcnt counts up count direction flag 1 note: * can only be written with 0, to clear the flag. [clearing conditions] when dtc is activated by tgia interrupt and disel bit in dtc s mrb register is 0 when dmac is activated by tgia interrupt and dta bit in dmac s dmabcr register is 1 when 0 is written to tgfa after reading tgfa = 1 [clearing conditions] when dtc is activated by tgib interrupt and disel bit in dtc s mrb register is 0 when 0 is written to tgfb after reading tgfb = 1 [setting conditions] when tcnt = tgra while tgra is functioning as output compare register when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register [setting conditions] when tcnt = tgrb while tgrb is functioning as output compare register when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register
511 tcnt4?imer counter 4 h'fe96 tpu4 bit initial value read/write 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 10 0 r/w 9 0 r/w 8 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w up/down-counter * note: * this timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. in other cases it functions as an up-counter. tgr4a?imer general register 4a h'fe98 tpu4 tgr4b?imer general register 4b h'fe9a tpu4 bit initial value read/write 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w
512 tcr5?imer control register 5 h'fea0 tpu5 bit initial value read/write 7 0 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w 0 tpsc0 0 r/w 0 1 0 1 0 1 internal clock: count on /1 internal clock: count on /4 internal clock: count on /16 internal clock: count on /64 external clock: count on tclka pin input external clock: count on tclkc pin input internal clock: count on /256 external clock: count on tclkd pin input time prescaler 0 1 0 1 0 1 0 1 0 1 0 1 count at rising edge count at falling edge count at both edges clock edge 0 tcnt clearing disabled tcnt cleared by tgra compare match/input capture tcnt cleared by tgrb compare match/input capture counter clear 0 1 10 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * note: this setting is invalid when channel 5 is in phase counting mode. note: this setting is invalid when channel 5 is in phase counting mode. note: * synchronous operation is selected by setting the sync bit in tsyr to 1.
513 tmdr5?imer mode register 5 h'fea1 tpu5 bit initial value read/write 7 1 6 1 5 0 4 0 3 md3 0 r/w 2 md2 0 r/w 1 md1 0 r/w 0 md0 0 r/w 0 0 normal operation reserved pwm mode 1 pwm mode 2 phase counting mode 1 phase counting mode 2 phase counting mode 3 phase counting mode 4 mode 1 1 * 0 1 0 1 * 0 1 0 1 0 1 0 1 * * : don t care note: md3 is a reserved bit. in a write, it should always be written with 0.
514 tior5?imer i/o control register 5 h'fea2 tpu5 bit initial value read/write 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w 0 ioa0 0 r/w 0 0 tgr5a i/o control 0 0 1 tgr5a is output compare register 10 1 100 1 10 1 * 1 0 0 tgr5a is input capture register 1 1 * output disabled initial output is 1 output output disabled initial output is 0 output capture input source is tioca5 pin 0 output at compare match 1 output at compare match toggle output at compare match * : don t care 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges 0 0 tgr5b i/o control 0 0 1 tgr5b is output compare register 10 1 100 1 10 1 * 1 0 0 tgr5b is input capture register 1 1 * output disabled initial output is 1 output output disabled initial output is 0 output capture input source is tiocb5 pin 0 output at compare match 1 output at compare match toggle output at compare match * : don t care 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges
515 tier5?imer interrupt enable register 5 h'fea4 tpu5 bit initial value read/write 7 ttge 0 r/w 6 1 5 tcieu 0 r/w 4 tciev 0 r/w 3 0 2 0 1 tgieb 0 r/w 0 tgiea 0 r/w 0 tgr interrupt enable a 1 0 tgr interrupt enable b 1 0 interrupt request (tciv) by tcfv disabled interrupt request (tciv) by tcfv enabled overflow interrupt enable 1 0 a/d conversion start request generation disabled a/d conversion start request generation enabled a/d conversion start request enable 1 0 interrupt request (tciu) by tcfu disabled interrupt request (tciu) by tcfu enabled underflow interrupt enable 1 interrupt request (tgia) by tgfa bit disabled interrupt request (tgia) by tgfa bit enabled interrupt request (tgib) by tgfb bit disabled interrupt request (tgib) by tgfb bit enabled
516 tsr5?imer status register 5 h'fea5 tpu5 bit initial value read/write 7 tcfd 1 r 6 1 5 tcfu 0 r/(w) * 4 tcfv 0 r/(w) * 3 0 2 0 1 tgfb 0 r/(w) * 0 tgfa 0 r/(w) * 0 input capture/output compare flag a 1 0 input capture/output compare flag b 1 0 [clearing condition] when 0 is written to tcfv after reading tcfv = 1 [setting condition] when the tcnt value overflows (from h'ffff to h'0000) overflow flag 1 0 [clearing condition] when 0 is written to tcfu after reading tcfu = 1 [setting condition] when the tcnt value underflows (from h'0000 to h'ffff) underflow flag 1 0 tcnt counts down tcnt counts up count direction flag 1 note: * can only be written with 0, to clear the flag. [clearing conditions] when dtc is activated by tgia interrupt and disel bit in dtc s mrb register is 0 when dmac is activated by tgia interrupt and dta bit in dmac s dmabcr register is 1 when 0 is written to tgfa after reading tgfa = 1 [clearing conditions] when dtc is activated by tgib interrupt and disel bit in dtc s mrb register is 0 when 0 is written to tgfb after reading tgfb = 1 [setting conditions] when tcnt = tgra while tgra is functioning as output compare register when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register [setting conditions] when tcnt = tgrb while tgrb is functioning as output compare register when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register
517 tcnt5?imer counter 5 h'fea6 tpu5 bit initial value read/write 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 10 0 r/w 9 0 r/w 8 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w up/down-counter * note: * this timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. in other cases it functions as an up-counter. tgr5a?imer general register 5a h'fea8 tpu5 tgr5b?imer general register 5b h'feaa tpu5 bit initial value read/write 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w
518 abwcr?us width control register h'fec0 bus controller bit modes 2, 4, 6 initial value read/write modes 1, 5, 7 initial value read/write 7 abw7 1 r/w 0 r/w 6 abw6 1 r/w 0 r/w 5 abw5 1 r/w 0 r/w 4 abw4 1 r/w 0 r/w 3 abw3 1 r/w 0 r/w 2 abw2 1 r/w 0 r/w 1 abw1 1 r/w 0 r/w 0 abw0 1 r/w 0 r/w 0 area n is designated as 16-bit access space area n is designated as 8-bit access space area 7 to 0 bus width control 1 (n = 15 to 0) astcr?ccess state control register h'fec1 bus controller bit initial value read/write 7 ast7 1 r/w 6 ast6 1 r/w 5 ast5 1 r/w 4 ast4 1 r/w 3 ast3 1 r/w 2 ast2 1 r/w 1 ast1 1 r/w 0 ast0 1 r/w 0 area n is designated as 2-state access space wait state insertion in area n external space accesses is disabled area n external space accesses are 3-state accesses wait state insertion in area n external space accesses is enabled area 7 to 0 access state control 1 (n = 7 to 0)
519 wtcra?ait control register a h'fec2 bus controller wtcrb?ait control register b h'fec4 bus controller wtcrb bit initial value read/write 15 0 r 14 w32 1 r/w 13 w31 1 r/w 12 w30 1 r/w 11 0 r 10 w22 1 r/w 9 w21 1 r/w 8 w20 1 r/w bit initial value read/write 7 0 r 6 w12 1 r/w 5 w11 1 r/w 4 w10 1 r/w 3 0 r 2 w02 1 r/w 1 w01 1 r/w 0 w00 1 r/w wtcra bit initial value read/write 15 0 r 14 w72 1 r/w 13 w71 1 r/w 12 w70 1 r/w 11 0 r 10 w62 1 r/w 9 w61 1 r/w 8 w60 1 r/w bit initial value read/write 7 0 r 6 w52 1 r/w 5 w51 1 r/w 4 w50 1 r/w 3 0 r 2 w42 1 r/w 1 w41 1 r/w 0 w40 1 r/w wait control 0 wn1 program wait not inserted in area n external access description 1 program wait state inserted in area n external access 0 wn2 1 2 program wait states inserted in area n external access 1 0 wn0 1 0 1 3 program wait states inserted in area n external access 0 0 4 program wait states inserted in area n external access 1 5 program wait states inserted in area n external access 1 0 6 program wait states inserted in area n external access 1 7 program wait states inserted in area n external access (n = 7 to 0)
520 rdncr?ead strobe timing control register h'fec6 bus controller bit initial value read/write 7 rdn7 0 r/w 6 rdn6 0 r/w 5 rdn5 0 r/w 4 rdn4 0 r/w 3 rdn3 0 r/w 2 rdn2 0 r/w 1 rdn1 0 r/w 0 rdn0 0 r/w read strobe timing control (n = 7 to 0) 0 in an area n read access, the rd strobe is negated at the end of the read cycle rdnn description 1 in an area n read access, the rd strobe is negated one half-state before the end of the read cycle
521 csacrh, csacrl cs assertion period control registers h'fec8 bus controller bit initial value read/write 15 csxh7 0 r/w 14 csxh6 0 r/w 13 csxh5 0 r/w 12 csxh4 0 r/w 11 csxh3 0 r/w 10 csxh2 0 r/w 9 csxh1 0 r/w 8 csxh0 0 r/w cs and address signal assertion period control 1 (n = 7 to 0) 0 in area n basic bus interface access, the csn and address assertion period (t h ) is not extended csxhn description 1 in area n basic bus interface access, the csn and address assertion period (t h ) is extended bit initial value read/write csacrh csacrl 7 csxt7 0 r/w 6 csxt6 0 r/w 5 csxt5 0 r/w 4 csxt4 0 r/w 3 csxt3 0 r/w 2 csxt2 0 r/w 1 csxt1 0 r/w 0 csxt0 0 r/w cs and address signal assertion period control 2 (n = 7 to 0) 0 in area n basic bus interface access, the csn and address assertion period (t t ) is not extended csxtn description 1 in area n basic bus interface access, the csn and address assertion period (t t ) is extended
522 bromcrh?rea 0 burst rom i/f control register h'feca bus controller bromcrl?rea 1 burst rom i/f control register h'fecb bus controller bit initial value read/write bromcrh 7 bsrm0 0 r/w 6 bsts02 0 r/w 5 bsts01 0 r/w 4 bsts00 0 r/w 3 0 r/w 2 0 r/w 1 bswd01 0 r/w 0 bswd00 0 r/w bit initial value read/write bromcrl 7 bsrm1 0 r/w 6 bsts12 0 r/w 5 bsts11 0 r/w 4 bsts10 0 r/w 3 0 r/w 2 0 r/w 1 bswd11 0 r/w 0 bswd10 0 r/w burst word length select bswdn1 0 1 bswdn0 0 1 0 1 description maximum 4 words in area n burst access maximum 8 words in area n burst access maximum 16 words in area n burst access maximum 32 words in area n burst access burst cycle select bstsn1 0 1 0 1 bstsn0 0 1 0 1 0 1 0 1 description area n burst cycle comprises 1 state area n burst cycle comprises 2 states area n burst cycle comprises 3 states area n burst cycle comprises 4 states area n burst cycle comprises 5 states area n burst cycle comprises 6 states area n burst cycle comprises 7 states area n burst cycle comprises 8 states bstsn2 0 1 (n = 1 or 0) (n = 1 or 0) burst rom interface select 0 area n is basic bus interface space bsrmn description 1 area n is burst rom interface space
523 bcr?us control register h'fecc bus controller bit initial value read/write 15 brle 0 r/w 14 breqoe 0 r/w 13 0 r/w 12 idlc 1 r/w 11 icis1 1 r/w 10 icis0 1 r/w 9 wdbe 0 r/w 8 waite 0 r/w bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w wait pin enable 0 wait input by wait pin disabled wait pin can be used as i/o port 1 wait input by wait pin enabled write data buffer enable 0 write data buffer function not used 1 write data buffer function used idle cycle insert 0 0 idle cycle not inserted when external read cycle and external write cycle are performed consecutively 1 idle cycle inserted when external read cycle and external write cycle are performed consecutively idle cycle insert 1 0 idle cycle not inserted in case of consecutive external read cycles in different areas 1 idle cycle inserted in case of consecutive external read cycles in different areas breqo pin enable 0 breqo signal output disabled breqo pin can be used as i/o port 1 breqo signal output enabled external bus release enable 0 external bus release disabled breq , back , and breqo pins can be used as i/o ports 1 external bus release enabled idle cycle state number select 0 idle cycle comprises 1 state 1 idle cycle comprises 2 states
524 ramer?am emulation register h'fece rom (f-ztat version only) bit initial value read/write 7 0 6 0 5 0 4 0 3 rams 0 r/w 2 ram2 0 r/w 1 ram1 0 r/w 0 ram0 0 r/w ram select, flash memory area select rams 0 1 ram area block name h'ffa000 to h'ffafff h'000000 to h'000fff h'001000 to h'001fff h'002000 to h'002fff h'003000 to h'003fff h'004000 to h'004fff h'005000 to h'005fff h'006000 to h'006fff h'007000 to h'007fff 4-kbyte ram area eb0 (4 kbytes) eb1 (4 kbytes) eb2 (4 kbytes) eb3 (4 kbytes) eb4 (4 kbytes) eb5 (4 kbytes) eb6 (4 kbytes) eb7 (4 kbytes) ram2 * 0 1 ram1 * 0 1 0 1 ram0 * 0 1 0 1 0 1 0 1 modes 5, 6, 13, 14 h'100000 to h'100fff h'101000 to h'101fff h'102000 to h'102fff h'103000 to h'103fff h'104000 to h'104fff h'105000 to h'105fff h'106000 to h'106fff h'107000 to h'107fff modes 4, 7, 10, 11, 12, 15
525 dramcr?ram control register h'fed0 bus controller bit initial value read/write 15 oee 0 r/w 14 rast 0 r/w 13 0 r/w 12 cast 0 r/w 11 0 r/w 10 rmts2 0 r/w 9 rmts1 0 r/w 8 rmts0 0 r/w dram space select rmts0 description area 5 area 4 area 3 area 2 0 normal space normal space dram space normal space dram space dram space reserved (setting prohibited) continuous dram space rmts1 0 rmts2 0 1 0 1 1 0 1 0 1 1 column address output cycle number select 0 column address output cycle comprises 2 states 1 column address output cycle comprises 3 states ras assertion timing select 0 ras is asserted from falling edge in t r cycle 1 ras is asserted from start of t r cycle oe output enable 0 oe signal output disabled oe pin can be used as i/o port 1 oe signal output enabled
526 bit initial value read/write 7 be 0 r/w 6 rcdm 0 r/w 5 dds 0 r/w 4 edds 0 r/w 3 0 r/w 2 mxc2 0 r/w 1 mxc1 0 r/w 0 mxc0 0 r/w address multiplex select 0 8-bit shift when 8-bit access space is designated: row address bits a23 to a8 used for comparison when 16-bit access space is designated: row address bits a23 to a9 used for comparison 0 1 9-bit shift when 8-bit access space is designated: row address bits a23 to a9 used for comparison when 16-bit access space is designated: row address bits a23 to a10 used for comparison 10-bit shift when 8-bit access space is designated: row address bits a23 to a10 used for comparison when 16-bit access space is designated: row address bits a23 to a11 used for comparison 11-bit shift when 8-bit access space is designated: row address bits a23 to a11 used for comparison when 16-bit access space is designated: row address bits a23 to a12 used for comparison reserved (setting prohibited) 0 1 0 1 1 exdmac single address transfer option 0 full access is always executed when exdmac single address transfer is performed in dram space 1 burst access is possible when exdmac single address transfer is performed in dram space dmac single address transfer option 0 full access is always executed when dmac single address transfer is performed in dram space 1 burst access is possible when dmac single address transfer is performed in dram space ras down mode 0 ras up mode selected for dram space access 1 ras down mode selected for dram space access burst access enable 0 full access always used for dram space access 1 dram space access performed in fast page mode
527 draccr?ram access control register h'fed2 bus controller bit initial value read/write 7 drmi 0 r/w 6 0 r/w 5 tpc1 0 r/w 4 tpc0 0 r/w 3 0 r/w 2 0 r/w 1 rcd1 0 r/w 0 rcd0 0 r/w ras - cas wait control 0 wait cycle not inserted between ras assert cycle and cas assert cycle 1 0 1 0 1 1-state wait cycle inserted between ras assert cycle and cas assert cycle 2-state wait cycle inserted between ras assert cycle and cas assert cycle 3-state wait cycle inserted between ras assert cycle and cas assert cycle precharge state control 0 ras precharge cycle comprises 1 state 1 0 1 0 1 ras precharge cycle comprises 2 states ras precharge cycle comprises 3 states ras precharge cycle comprises 4 states idle cycle insertion 0 idle cycle not inserted after dram space access 1 idle cycle inserted after dram space access idle cycle insertion conditions, setting of number of states, etc., comply with settings of bits icis1, icis0, and idlc in bcr register
528 refcr?efresh control register h'fed4 bus controller bit initial value read/write 15 cmf 0 r/(w) * 14 cmie 0 r/w 13 rcw1 0 r/w 12 rcw0 0 r/w 11 0 r/w 10 rtck2 0 r/w 9 rtck1 0 r/w 8 rtck0 0 r/w refresh counter clock select 0 count operation halted 1 0 1 count on /2 count on /8 count on /32 count on /128 count on /512 0 1 0 1 00 1 count on /2048 10 count on /4096 1 cas - ras wait control 0 wait state not inserted between cas and ras in refresh cycle 1 0 1 0 1 1 wait state inserted between cas and ras in refresh cycle 2 wait states inserted between cas and ras in refresh cycle 3 wait states inserted between cas and ras in refresh cycle compare match interrupt enable 0 interrupt request by cmf flag disabled 1 interrupt request by cmf flag enabled compare match flag 0 [clearing conditions] when 0 is written to cmf after reading cmf = 1 while the rfshe bit is cleared to 0 when cbr refreshing is executed while the rfshe bit is set to 1 1 [setting condition] when rtcor = rtcnt note: * only 0 can be written, to clear the flag.
529 bit initial value read/write 7 rfshe 0 r/w 6 cbrm 0 r/w 5 rlw1 0 r/w 4 rlw0 0 r/w 3 slfrf 0 r/w 2 tpcs2 0 r/w 1 tpcs1 0 r/w 0 tpcs0 0 r/w self-refresh precharge cycle control 0 ras precharge cycle after self-refresh = [tpc set value] states 0 1 1 0 1 ras precharge cycle after self-refresh = [tpc set value + 1] states ras precharge cycle after self-refresh = [tpc set value + 2] states ras precharge cycle after self-refresh = [tpc set value + 3] states ras precharge cycle after self-refresh = [tpc set value + 4] states ras precharge cycle after self-refresh = [tpc set value + 5] states 0 1 0 1 00 1 ras precharge cycle after self-refresh = [tpc set value + 6] states 10 ras precharge cycle after self-refresh = [tpc set value + 7] states 1 self-refresh enable 0 self-refreshing is disabled in software standby mode 1 self-refreshing is enabled in software standby mode refresh cycle wait control 0 no wait state inserted in cbr refresh 1 0 1 0 1 1 wait state inserted in cbr refresh 2 wait states inserted in cbr refresh 3 wait states inserted in cbr refresh cbr refresh mode 0 external access during cas-before-ras refreshing is enabled 1 external access during cas-before-ras refreshing is disabled refresh control 0 refresh control is not performed 1 refresh control is performed
530 rtcnt?efresh timer counter h'fed6 bus controller bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w count value based on internal clock rtcor?efresh time control register h'fed7 bus controller bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w period for compare match operations with rtcnt
531 mar0ah?emory address register 0ah h'fee0 dmac mar0al?emory address register 0al h'fee2 dmac * : undefined bit mar0al initial value read/write 15 * r/w 14 * r/w 13 * r/w 12 * r/w 11 * r/w 10 * r/w 9 * r/w 8 * r/w 7 * r/w 6 * r/w 5 * r/w 4 * r/w 3 * r/w 2 * r/w 1 * r/w 0 * r/w bit mar0ah initial value read/write 31 0 30 0 29 0 28 0 27 0 26 0 25 0 24 0 23 * r/w 22 * r/w 21 * r/w 20 * r/w 19 * r/w 18 * r/w 17 * r/w 16 * r/w in short address mode: specifies transfer destination/transfer source address in full address mode: specifies transfer source address ioar0a?/o address register 0a h'fee4 dmac * : undefined bit ioar0a initial value read/write 15 * r/w 14 * r/w 13 * r/w 12 * r/w 11 * r/w 10 * r/w 9 * r/w 8 * r/w 7 * r/w 6 * r/w 5 * r/w 4 * r/w 3 * r/w 2 * r/w 1 * r/w 0 * r/w in short address mode: specifies transfer destination/transfer source address in full address mode: not used
532 etcr0a?ransfer count register 0a h'fee6 dmac * : undefined bit etcr0a initial value read/write sequential mode and idle mode normal mode repeat mode block transfer mode 15 * r/w 14 * r/w 13 * r/w 12 * r/w 11 * r/w 10 * r/w 9 * r/w 8 * r/w 7 * r/w 6 * r/w 5 * r/w 4 * r/w 3 * r/w 2 * r/w 1 * r/w 0 * r/w transfer counter block size counter transfer counter holds number of transfers holds block size mar0bh?emory address register 0bh h'fee8 dmac mar0bl?emory address register 0bl h'feea dmac * : undefined bit mar0bl initial value read/write 15 * r/w 14 * r/w 13 * r/w 12 * r/w 11 * r/w 10 * r/w 9 * r/w 8 * r/w 7 * r/w 6 * r/w 5 * r/w 4 * r/w 3 * r/w 2 * r/w 1 * r/w 0 * r/w bit mar0bh initial value read/write 31 0 30 0 29 0 28 0 27 0 26 0 25 0 24 0 23 * r/w 22 * r/w 21 * r/w 20 * r/w 19 * r/w 18 * r/w 17 * r/w 16 * r/w in short address mode: specifies transfer destination/transfer source address in full address mode: specifies transfer destination
533 ioar0b?/o address register 0b h'feec dmac * : undefined bit ioar0b initial value read/write 15 * r/w 14 * r/w 13 * r/w 12 * r/w 11 * r/w 10 * r/w 9 * r/w 8 * r/w 7 * r/w 6 * r/w 5 * r/w 4 * r/w 3 * r/w 2 * r/w 1 * r/w 0 * r/w in short address mode: specifies transfer destination/transfer source address in full address mode: not used etcr0b?ransfer count register 0b h'feee dmac * : undefined note: not used in normal mode. bit etcr0b initial value read/write sequential mode and idle mode repeat mode block transfer mode 15 * r/w 14 * r/w 13 * r/w 12 * r/w 11 * r/w 10 * r/w 9 * r/w 8 * r/w 7 * r/w 6 * r/w 5 * r/w 4 * r/w 3 * r/w 2 * r/w 1 * r/w 0 * r/w transfer counter transfer counter holds number of transfers block transfer counter
534 mar1ah?emory address register 1ah h'fef0 dmac mar1al?emory address register 1al h'fef2 dmac * : undefined bit mar1al initial value read/write 15 * r/w 14 * r/w 13 * r/w 12 * r/w 11 * r/w 10 * r/w 9 * r/w 8 * r/w 7 * r/w 6 * r/w 5 * r/w 4 * r/w 3 * r/w 2 * r/w 1 * r/w 0 * r/w bit mar1ah initial value read/write 31 0 30 0 29 0 28 0 27 0 26 0 25 0 24 0 23 * r/w 22 * r/w 21 * r/w 20 * r/w 19 * r/w 18 * r/w 17 * r/w 16 * r/w in short address mode: specifies transfer destination/transfer source address in full address mode: not used ioar1a?/o address register 1a h'fef4 dmac * : undefined bit ioar1a initial value read/write 15 * r/w 14 * r/w 13 * r/w 12 * r/w 11 * r/w 10 * r/w 9 * r/w 8 * r/w 7 * r/w 6 * r/w 5 * r/w 4 * r/w 3 * r/w 2 * r/w 1 * r/w 0 * r/w in short address mode: specifies transfer destination/transfer source address in full address mode: not used
535 etcr1a?ransfer count register 1a h'fef6 dmac * : undefined bit etcr1a initial value read/write sequential mode idle mode normal mode repeat mode block transfer mode 15 * r/w 14 * r/w 13 * r/w 12 * r/w 11 * r/w 10 * r/w 9 * r/w 8 * r/w 7 * r/w 6 * r/w 5 * r/w 4 * r/w 3 * r/w 2 * r/w 1 * r/w 0 * r/w transfer counter block size counter transfer counter holds number of transfers holds block size mar1bh?emory address register 1bh h'fef8 dmac mar1bl?emory address register 1bl h'fefa dmac * : undefined bit mar1bl initial value read/write 15 * r/w 14 * r/w 13 * r/w 12 * r/w 11 * r/w 10 * r/w 9 * r/w 8 * r/w 7 * r/w 6 * r/w 5 * r/w 4 * r/w 3 * r/w 2 * r/w 1 * r/w 0 * r/w bit mar1bh initial value read/write 31 0 30 0 29 0 28 0 27 0 26 0 25 0 24 0 23 * r/w 22 * r/w 21 * r/w 20 * r/w 19 * r/w 18 * r/w 17 * r/w 16 * r/w in short address mode: specifies transfer destination/transfer source address in full address mode: not used
536 ioar1b?/o address register 1b h'fefc dmac * : undefined bit ioar1b initial value read/write 15 * r/w 14 * r/w 13 * r/w 12 * r/w 11 * r/w 10 * r/w 9 * r/w 8 * r/w 7 * r/w 6 * r/w 5 * r/w 4 * r/w 3 * r/w 2 * r/w 1 * r/w 0 * r/w in short address mode: specifies transfer destination/transfer source address in full address mode: not used etcr1b?ransfer count register 1b h'fefe dmac * : undefined note: not used in normal mode. bit etcr1b initial value read/write sequential mode and idle mode repeat mode block transfer mode 15 * r/w 14 * r/w 13 * r/w 12 * r/w 11 * r/w 10 * r/w 9 * r/w 8 * r/w 7 * r/w 6 * r/w 5 * r/w 4 * r/w 3 * r/w 2 * r/w 1 * r/w 0 * r/w transfer counter transfer counter holds number of transfers block transfer counter
537 dmawer?ma write enable register h'ff20 dmac bit dmawer initial value read/write 7 0 6 0 5 0 4 0 3 we1b 0 r/w 2 we1a 0 r/w 1 we0b 0 r/w 0 we0a 0 r/w write enable 0a 0 writes to all bits in dmacr0a, and bits 8, 4, and 0 in dmabcr are disabled 1 writes to all bits in dmacr0a, and bits 8, 4, and 0 in dmabcr are enabled write enable 0b 0 writes to all bits in dmacr0b, bits 9, 5, and 1 in dmabcr, and bit 4 in dmatcr are disabled 1 writes to all bits in dmacr0b, bits 9, 5, and 1 in dmabcr, and bit 4 in dmatcr are enabled write enable 1a 0 writes to all bits in dmacr1a, and bits 10, 6, and 2 in dmabcr are disabled 1 writes to all bits in dmacr1a, and bits 10, 6, and 2 in dmabcr are enabled write enable 1b 0 writes to all bits in dmacr1b, bits 11, 7, and 3 in dmabcr, and bit 5 in dmatcr are disabled 1 writes to all bits in dmacr1b, bits 11, 7, and 3 in dmabcr, and bit 5 in dmatcr are enabled
538 dmatcr?ma terminal control register h'ff21 dmac bit dmatcr initial value read/write 7 0 6 0 5 tee1 0 r/w 4 tee0 0 r/w 3 0 2 0 1 0 0 0 tend0 pin enable 0 tend0 pin output disabled 1 tend0 pin output enabled tend 1 pin enable 0 tend1 pin output disabled 1 tend1 pin output enabled
539 dmacr0a?ma control register 0a h'ff22 dmac dmacr1a?ma control register 1a h'ff24 dmac dmacr0b?ma control register 0b h'ff23 dmac dmacr1b?ma control register 1b h'ff25 dmac full address mode dmacra bit dmacra initial value read/write 15 dtsz 0 r/w 14 said 0 r/w 13 saide 0 r/w 12 blkdir 0 r/w 11 blke 0 r/w 10 0 r/w 9 0 r/w 8 0 r/w block direction/block enable 0 transfer in normal mode 1 0 1 0 1 transfer in block transfer mode, destination is block area transfer in normal mode transfer in block transfer mode, source is block area source address increment/decrement 0 mara is fixed 1 0 1 0 1 mara is incremented after a data transfer (1) when dtsz = 0, mara is incremented by 1 after a transfer (2) when dtsz = 1, mara is incremented by 2 after a transfer mara is fixed mara is decremented after a data transfer (1) when dtsz = 0, mara is decremented by 1 after a transfer (2) when dtsz = 1, mara is decremented by 2 after a transfer data transfer size 0 byte-size transfer 1 word-size transfer
540 full address mode dmacrb bit dmacrb initial value read/write 7 0 r/w 6 daid 0 r/w 5 daide 0 r/w 4 0 r/w 3 dtf3 0 r/w 2 dtf2 0 r/w 1 dtf1 0 r/w 0 dtf0 0 r/w data transfer factor dtf3 dtf2 dtf1 dtf0 block transfer mode normal mode a/d converter conversion end interrupt dreq pin falling edge input dreq pin low-level input sci channel 0 transmission complete interrupt sci channel 0 reception complete interrupt 0 1 0 1 0 1 sci channel 1 transmission complete interrupt 0 sci channel 1 reception complete interrupt dreq pin falling edge input dreq pin low-level input auto-request (cycle steal) auto-request (burst) 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 0 1 1 1 1 tpu channel 0 compare match/ input capture a interrupt tpu channel 1 compare match/ input capture a interrupt tpu channel 2 compare match/ input capture a interrupt tpu channel 3 compare match/ input capture a interrupt tpu channel 4 compare match/ input capture a interrupt tpu channel 5 compare match/ input capture a interrupt * : don t care destination address increment/decrement 0 marb is fixed 1 0 1 0 1 marb is incremented after a data transfer (1) when dtsz = 0, marb is incremented by 1 after a transfer (2) when dtsz = 1, marb is incremented by 2 after a transfer marb is fixed marb is decremented after a data transfer (1) when dtsz = 0, marb is decremented by 1 after a transfer (2) when dtsz = 1, marb is decremented by 2 after a transfer
541 short address mode bit dmacr initial value read/write 7 dtsz 0 r/w 6 dtid 0 r/w 5 rpe 0 r/w 4 dtdir 0 r/w 3 dtf3 0 r/w 2 dtf2 0 r/w 1 dtf1 0 r/w 0 dtf0 0 r/w data transfer factor 0 channel a channel b 1 0 1 activated by a/d converter conversion end interrupt activated by dreq pin falling edge input activated by dreq pin low-level input activated by sci channel 0 transmission complete interrupt activated by sci channel 0 reception complete interrupt 0 1 0 1 00 1 activated by sci channel 1 transmission complete interrupt 10 activated by sci channel 1 reception complete interrupt 1 0 0 1 activated by tpu channel 0 compare match/ input capture a interrupt 1 0 1 activated by tpu channel 1 compare match/ input capture a interrupt activated by tpu channel 2 compare match/ input capture a interrupt activated by tpu channel 3 compare match/ input capture a interrupt activated by tpu channel 4 compare match/ input capture a interrupt activated by tpu channel 5 compare match/ input capture a interrupt 0 1 0 1 00 1 10 1 data transfer direction 0 dual address mode: transfer with mar as source address and ioar as destination address single address mode: transfer with mar as source address and dack pin as write strobe 1 dual address mode: transfer with ioar as source address and mar as destination address single address mode: transfer with dack as read strobe and mar as destination address repeat enable 0 sequential mode 1 repeat mode or idle mode data transfer increment/ decrement 0 mar is incremented after a data transfer 1 mar is decremented after a data transfer data transfer size 0 byte-size transfer 1 word-size transfer
542 dmabcrh?ma band control register h'ff26 dmac dmabcrl?ma band control register h'ff27 dmac full address mode dmabcrh bit dmabcrh initial value read/write 15 fae1 0 r/w 14 fae0 0 r/w 13 0 r/w 12 0 r/w 11 dta1 0 r/w 10 0 r/w 9 dta0 0 r/w 8 0 r/w channel 0 data transfer acknowledge 0 clearing of selected internal interrupt source at time of dma transfer is disabled 1 clearing of selected internal interrupt source at time of dma transfer is enabled channel 1 data transfer acknowledge 0 clearing of selected internal interrupt source at time of dma transfer is disabled 1 clearing of selected internal interrupt source at time of dma transfer is enabled channel 0 full address enable 0 short address mode 1 full address mode channel 1 full address enable 0 short address mode 1 full address mode
543 full address mode dmabcrl bit dmabcrl initial value read/write 7 dtme1 0 r/w 6 dte1 0 r/w 5 dtme0 0 r/w 4 dte0 0 r/w 3 dtie1b 0 r/w 2 dtie1a 0 r/w 1 dtie0b 0 r/w 0 dtie0a 0 r/w channel 0 data transfer interrupt enable a 0 transfer end interrupt disabled 1 transfer end interrupt enabled channel 0 data transfer interrupt enable b 0 transfer suspended interrupt disabled 1 transfer suspended interrupt enabled channel 1 data transfer interrupt enable a 0 transfer end interrupt disabled 1 transfer end interrupt enabled channel 1 data transfer interrupt enable b 0 transfer suspended interrupt disabled 1 transfer suspended interrupt enabled channel 0 data transfer enable 0 data transfer disabled 1 data transfer enabled channel 1 data transfer enable 0 data transfer disabled 1 data transfer enabled channel 0 data transfer master enable 0 data transfer disabled. in burst mode, cleared to 0 by an nmi interrupt 1 data transfer enabled channel 1 data transfer master enable 0 data transfer disabled. in burst mode, cleared to 0 by an nmi interrupt 1 data transfer enabled
544 short address mode dmabcrh bit dmabcrh initial value read/write 15 fae1 0 r/w 14 fae0 0 r/w 13 sae1 0 r/w 12 sae0 0 r/w 11 dta1b 0 r/w 10 dta1a 0 r/w 9 dta0b 0 r/w 8 dta0a 0 r/w channel 0a data transfer acknowledge 0 clearing of selected internal interrupt source at time of dma transfer is disabled 1 clearing of selected internal interrupt source at time of dma transfer is enabled channel 0b data transfer acknowledge 0 clearing of selected internal interrupt source at time of dma transfer is disabled 1 clearing of selected internal interrupt source at time of dma transfer is enabled channel 1a data transfer acknowledge 0 clearing of selected internal interrupt source at time of dma transfer is disabled 1 clearing of selected internal interrupt source at time of dma transfer is enabled channel 1b data transfer acknowledge 0 clearing of selected internal interrupt source at time of dma transfer is disabled 1 clearing of selected internal interrupt source at time of dma transfer is enabled channel 0b single address enable 0 transfer in dual address mode 1 transfer in single address mode channel 1b single address enable 0 transfer in dual address mode 1 transfer in single address mode channel 0 full address mode 0 short address mode 1 full address mode channel 1 full address mode 0 short address mode 1 full address mode
545 short address mode dmabcrl bit dmabcrl initial value read/write 7 dte1b 0 r/w 6 dte1a 0 r/w 5 dte0b 0 r/w 4 dte0a 0 r/w 3 dtie1b 0 r/w 2 dtie1a 0 r/w 1 dtie0b 0 r/w 0 dtie0a 0 r/w channel 0a data transfer interrupt enable 0 transfer end interrupt disabled 1 transfer end interrupt enabled channel 0b data transfer interrupt enable 0 transfer end interrupt disabled 1 transfer end interrupt enabled channel 1a data transfer interrupt enable 0 transfer end interrupt disabled 1 transfer end interrupt enabled channel 1b data transfer interrupt enable 0 transfer end interrupt disabled 1 transfer end interrupt enabled channel 0a data transfer enable 0 data transfer disabled 1 data transfer enabled channel 1a data transfer enable 0 data transfer disabled 1 data transfer enabled channel 0b data transfer enable 0 data transfer disabled 1 data transfer enabled channel 1b data transfer enable 0 data transfer disabled 1 data transfer enabled
546 dtcer?tc enable register h'ff28 to h'ff2f dtc bit initial value read/write 7 dtce7 0 r/w 6 dtce6 0 r/w 5 dtce5 0 r/w 4 dtce4 0 r/w 3 dtce3 0 r/w 2 dtce2 0 r/w 1 dtce1 0 r/w 0 dtce0 0 r/w 0 dtc activation enable 1 register bits 7 irq0 irq8 tgi2a tgi5a dmtend0a rxi2 correspondence between interrupt sources and dtcer register bits dtcera dtcerb dtcerc dtcerd dtcere dtcerf dtcerg dtcerh 6 irq1 irq9 adi tgi2b tgi5b dmtend0b txi2 5 irq2 irq10 tgi0a tgi3a dmtend1a rxi3 4 irq3 irq11 tgi0b tgi3b dmtend1b txi3 3 irq4 irq12 tgi0c tgi3c cmia0 rxi0 rxi4 2 irq5 irq13 tgi0d tgi3d cmib0 txi0 txi4 1 irq6 irq14 tgi1a tgi4a cmia1 rxi1 0 irq7 irq15 tgi1b tgi4b cmib1 txi1 dtc activation by interrupt is disabled [clearing conditions] when data transfer ends with the disel bit set to 1 when the specified number of transfers end dtc activation by this interrupt is enabled [hold condition] when the disel bit is 0 and the specified number of transfers have not ended note: for dtce bit setting, bit manipulation instructions such as bset and bclr must be used for reading and writing. for the initial setting only, however, when setting multiple activation sources at one time, it is possible to disable interrupts and write to the relevant register after a dummy read.
547 dtvecr?tc vector register h'ff30 dtc bit initial value read/write 7 swdte 0 r/(w) * 1 6 dtvec6 0 r/(w) * 2 5 dtvec5 0 r/(w) * 2 4 dtvec4 0 r/(w) * 2 3 dtvec3 0 r/(w) * 2 2 dtvec2 0 r/(w) * 2 1 dtvec1 0 r/(w) * 2 0 dtvec0 0 r/(w) * 2 sets vector number for dtc software activation 0 dtc software activation is disabled [clearing conditions] when the disel bit is 0 and the specified number of transfers have not ended after an swdtend request dtc software activation is enabled [hold conditions] when data transfer ends with the disel bit set to 1 when the specified number of transfers end during software-activated data transfer dtc software activation enable 1 notes: 1. only 1 can be written to the swdte bit. 2. bits dtvec6 to dtvec0 can be written to when swdte = 0.
548 intcr?nterrupt control register h'ff31 interrupt controller bit initial value read/write 7 0 6 0 5 intm1 0 r/w 4 intm0 0 r/w 3 nmieg 0 r/w 2 0 1 0 0 0 nmi edge select 0 interrupt request generated at falling edge of nmi input 1 interrupt request generated at rising edge of nmi input interrupt control mode 1 and 0 0 1 0 1 interrupts are controlled by i bit setting prohibited interrupts are controlled by bits i2 to i0, and ipr setting prohibited intm1 description 0 2 interrupt control mode 0 1 intm2 ier?rq enable register h'ff32 interrupt controller bit initial value read/write 15 irq15e 0 r/w 14 irq14e 0 r/w 13 irq13e 0 r/w 12 irq12e 0 r/w 11 irq11e 0 r/w 10 irq10e 0 r/w 9 irq9e 0 r/w 8 irq8e 0 r/w bit initial value read/write 7 irq7e 0 r/w 6 irq6e 0 r/w 5 irq5e 0 r/w 4 irq4e 0 r/w 3 irq3e 0 r/w 2 irq2e 0 r/w 1 irq1e 0 r/w 0 irq0e 0 r/w irq15 to irq0 enable 0 irqn interrupts disabled 1 irqn interrupts enabled (n = 15 to 0)
549 isr?rq status register h'ff34 interrupt controller bit initial value read/write 15 irq15f 0 r/(w) * 14 irq14f 0 r/(w) * 13 irq13f 0 r/(w) * 12 irq12f 0 r/(w) * 11 irq11f 0 r/(w) * 10 irq10f 0 r/(w) * 9 irq9f 0 r/(w) * 8 irq8f 0 r/(w) * bit initial value read/write 7 irq7f 0 r/(w) * 6 irq6f 0 r/(w) * 5 irq5f 0 r/(w) * 4 irq4f 0 r/(w) * 3 irq3f 0 r/(w) * 2 irq2f 0 r/(w) * 1 irq1f 0 r/(w) * 0 irq0f 0 r/(w) * irq15 to irq0 flags 0 [clearing conditions] when 0 is written to irqnf after reading irqnf = 1 when interrupt exception handling is executed when low-level detection is set (irqnscb = irqnsca = 0) and irqn input is high when irqn interrupt exception handling is executed when falling, rising, or both-edge detection is set (irqnscb = 1 or irqnsca = 1) when the dtc is activated by an irqn interrupt and the disel bit in mrb of the dtc is 0 1 [setting conditions] when irqn input goes low when low-level detection is set (irqnscb = irqnsca = 0) when a falling edge occurs in irqn input when falling edge detection is set (irqnscb = 0, irqnsca = 1) when a rising edge occurs in irqn input when rising edge detection is set (irqnscb = 1, irqnsca = 0) when a falling or rising edge occurs in irqn input when both-edge detection is set (irqnscb = irqnsca = 1) (n = 15 to 0) note: * can only be written with 0, to clear the flag.
550 sbycr?tandby control register h'ff3a system control bit initial value read/write 7 ssby 0 r/w 6 ope 1 r/w 5 0 4 0 3 sts3 1 r/w 2 sts2 1 r/w 1 sts1 1 r/w 0 sts0 1 r/w standby timer select 3 to 0 0 reserved 1 0 1 reserved reserved reserved reserved standby time = 64 states standby time = 512 states standby time = 1,024 states standby time = 2,048 states standby time = 4,096 states standby time = 16,384 states standby time = 32,768 states standby time = 65,536 states standby time = 131,072 states standby time = 262,144 states standby time = 524,288 states 0 1 0 1 00 1 10 1 0 0 1 1 0 1 0 1 0 1 00 1 10 1 output port enable 0 in software standby mode, address bus and bus control signals are high-impedance 1 in software standby mode, address bus and bus control signals retain output state software standby 0 transition to sleep mode after execution of sleep instruction 1 transition to software standby mode after execution of sleep instruction note: in the f-ztat version, the flash memory oscillation settling time must be secured.
551 sckcr?ystem clock control register h'ff3b system control bit initial value read/write 7 pstop 0 r/w 6 0 r/w 5 0 4 0 3 stcs 0 r/w 2 sck2 0 r/w 1 sck1 0 r/w 0 sck0 0 r/w 0 0 1/1 1/2 1/4 1/8 1/16 1/32 system clock select 2 to 0 1 1 0 1 setting prohibited 0 1 0 1 1 1 0 specified multiplication factor is valid after transition to software standby mode specified multiplication factor is valid immediately after stc bits are rewritten frequency multiplication factor switching mode select 1 0 1 clock output control output fixed high output fixed high fixed high fixed high high impedance high impedance pstop normal operation sleep mode software standby mode hardware standby mode
552 syscr?ystem control register h'ff3d system control bit initial value read/write 7 1 r/w 6 1 r/w 5 macs 0 r/w 4 0 r/w 3 flshe 0 r/w 2 0 1 expe * r/w 0 rame 1 r/w 0 on-chip ram disabled on-chip ram enabled ram enable 1 0 external bus disabled external bus enabled external bus mode enable 1 0 flash memory control registers are not selected for area h'ffffc8 to h'ffffcb flash memory control registers are selected for area h'ffffc8 to h'ffffcb flash memory control register enable 1 0 non-saturating calculation for mac instruction saturating calculation for mac instruction mac saturation 1 note: * determined by pins md2 to md0. mdcr?ode control register h'ff3e mcu bit initial value read/write 7 0 6 0 5 0 4 0 3 0 2 mds2 * r 1 mds1 * r 0 mds0 * r current operating mode designated by mode pins note: * determined by pins md2 to md0.
553 mstpcrh?odule stop control register h h'ff40 power-down state mstpcrl?odule stop control register l h'ff41 power-down state 15 0 r/w bit initial value read/write 14 0 r/w 13 0 r/w 12 0 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w mstpcrh mstpcrl specify module stop mode 0 module stop mode cleared 1 module stop mode set all-module-clocks-stop mode enable 0 all-module-clocks-stop mode disabled 1 all-module-clocks-stop mode enabled acse mstp14 mstp13 mstp12 mstp11 mstp10 mstp9 mstp8 mstp7 mstp6 mstp5 mstp4 mstp3 mstp2 mstp1 mstp0 all-module-clocks-stop enable exdmac dmac dtc tpu ppg d/a0, 1 d/a2, 3 a/d sci2 sci1 sci0 8-bit timer mstpcrh mstpcrl register bit module correspondence between mstp bits and on-chip supporting functions
554 pllcr?ll control register h'ff45 clock pulse generator bit initial value read/write 7 0 6 0 5 0 4 0 3 0 r/w 2 0 1 stc1 0 r/w 0 stc0 0 r/w frequency multiplication factor 0 1 1 0 1 0 1 2 4 setting prohibited
555 pcr?pg output control register h'ff46 ppg bit initial value read/write 7 g3cms1 1 r/w 6 g3cms0 1 r/w 5 g2cms1 1 r/w 4 g2cms0 1 r/w 3 g1cms1 1 r/w 2 g1cms0 1 r/w 1 g0cms1 1 r/w 0 g0cms0 1 r/w 0 0 tpu channel 0 compare match tpu channel 1 compare match pulse output group 0 output trigger select 1 10 1 tpu channel 2 compare match tpu channel 3 compare match 0 0 tpu channel 0 compare match tpu channel 1 compare match tpu channel 2 compare match tpu channel 3 compare match pulse output group 1 output trigger select 1 10 1 0 0 tpu channel 0 compare match tpu channel 1 compare match tpu channel 2 compare match tpu channel 3 compare match pulse output group 2 output trigger select 1 10 1 0 0 tpu channel 0 compare match tpu channel 1 compare match tpu channel 2 compare match tpu channel 3 compare match pulse output group 3 output trigger select 1 10 1
556 pmr?pg output mode register h'ff47 ppg bit initial value read/write 7 g3inv 1 r/w 6 g2inv 1 r/w 5 g1inv 1 r/w 4 g0inv 1 r/w 3 g3nov 0 r/w 2 g2nov 0 r/w 1 g1nov 0 r/w 0 g0nov 0 r/w group n non-overlap 0 normal operation in pulse output group 0 (output values updated at compare match a in the selected tpu channel) 1 non-overlapping operation in pulse output group n (1 output and 0 output can be performed independently at compare match a and b in the selected tpu channel) (n = 3 to 0) group n invert 0 inverted output for pulse output group n (low-level output at pin for a 1 in podrh) 1 direct output for pulse output group n (high-level output at pin for a 1 in podrh) (n = 3 to 0)
557 nderh?ext data enable register h h'ff48 ppg nderl?ext data enable register l h'ff49 ppg bit initial value read/write nderh 7 nder15 0 r/w 6 nder14 0 r/w 5 nder13 0 r/w 4 nder12 0 r/w 3 nder11 0 r/w 2 nder10 0 r/w 1 nder9 0 r/w 0 nder8 0 r/w 0 pulse outputs po15 to po8 are disabled pulse outputs po15 to po8 are enabled next data enable 1 bit initial value read/write nderl 7 nder7 0 r/w 6 nder6 0 r/w 5 nder5 0 r/w 4 nder4 0 r/w 3 nder3 0 r/w 2 nder2 0 r/w 1 nder1 0 r/w 0 nder0 0 r/w 0 pulse outputs po7 to po0 are disabled pulse outputs po7 to po0 are enabled next data enable 1
558 podrh?utput data register h h'ff4a ppg podrl?utput data register l h'ff4b ppg bit initial value read/write podrh 7 pod15 0 r/(w) * 6 pod14 0 r/(w) * 5 pod13 0 r/(w) * 4 pod12 0 r/(w) * 3 pod11 0 r/(w) * 2 pod10 0 r/(w) * 1 pod9 0 r/(w) * 0 pod8 0 r/(w) * holds output data when pulse output is used bit initial value read/write podrl 7 pod7 0 r/(w) * 6 pod6 0 r/(w) * 5 pod5 0 r/(w) * 4 pod4 0 r/(w) * 3 pod3 0 r/(w) * 2 pod2 0 r/(w) * 1 pod1 0 r/(w) * 0 pod0 0 r/(w) * holds output data when pulse output is used note: * a bit that has been set for pulse output in nder is read-only.
559 ndrh?ext data register h h'ff4c (ff4e) ppg 1. when pulse output group output triggers are the same a. address: h'ff4c bit initial value read/write 7 ndr15 0 r/w 6 ndr14 0 r/w 5 ndr13 0 r/w 4 ndr12 0 r/w 3 ndr11 0 r/w 2 ndr10 0 r/w 1 ndr9 0 r/w 0 ndr8 0 r/w holds next data for pulse output groups 3 and 2 b. address: h'ff4e bit initial value read/write 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 2. when pulse output group output triggers are different a. address: h'ff4c bit initial value read/write 7 ndr15 0 r/w 6 ndr14 0 r/w 5 ndr13 0 r/w 4 ndr12 0 r/w 3 1 2 1 1 1 0 1 holds next data for pulse output group 3 b. address: h'ff4e bit initial value read/write 7 1 6 1 5 1 4 1 3 ndr11 0 r/w 2 ndr10 0 r/w 1 ndr9 0 r/w 0 ndr8 0 r/w holds next data for pulse output group 2
560 ndrl?ext data register l h'ff4d (ff4f) ppg 1. when pulse output group output triggers are the same a. address: h'ff4d bit initial value read/write 7 ndr7 0 r/w 6 ndr6 0 r/w 5 ndr5 0 r/w 4 ndr4 0 r/w 3 ndr3 0 r/w 2 ndr2 0 r/w 1 ndr1 0 r/w 0 ndr0 0 r/w holds next data for pulse output groups 1 and 0 b. address: h'ff4f bit initial value read/write 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 2. when pulse output group output triggers are different a. address: h'ff4d bit initial value read/write 7 ndr7 0 r/w 6 ndr6 0 r/w 5 ndr5 0 r/w 4 ndr4 0 r/w 3 1 2 1 1 1 0 1 holds next data for pulse output group 1 b. address: h'ff4f bit initial value read/write 7 1 6 1 5 1 4 1 3 ndr3 0 r/w 2 ndr2 0 r/w 1 ndr1 0 r/w 0 ndr0 0 r/w holds next data for pulse output group 0
561 port1?ort 1 register h'ff50 port 1 bit initial value read/write 7 p17 * r 6 p16 * r 5 p15 * r 4 p14 * r 3 p13 * r 2 p12 * r 1 p11 * r 0 p10 * r state of port 1 pins note: * determined by the state of pins p17 to p10. port2?ort 2 register h'ff51 port 2 bit initial value read/write 7 p27 * r 6 p26 * r 5 p25 * r 4 p24 * r 3 p23 * r 2 p22 * r 1 p21 * r 0 p20 * r state of port 2 pins note: * determined by the state of pins p27 to p20. port3?ort 3 register h'ff52 port 3 bit initial value read/write 7 0 6 0 5 p35 * r 4 p34 * r 3 p33 * r 2 p32 * r 1 p31 * r 0 p30 * r state of port 3 pins note: * determined by the state of pins p35 to p30.
562 port4?ort 4 register h'ff53 port 4 bit initial value read/write 7 p47 * r 6 p46 * r 5 p45 * r 4 p44 * r 3 p43 * r 2 p42 * r 1 p41 * r 0 p40 * r state of port 4 pins note: * determined by the state of pins p47 to p40. port5?ort 5 register h'ff54 port 5 bit initial value read/write 7 p57 * r 6 p56 * r 5 p55 * r 4 p54 * r 3 p53 * r 2 p52 * r 1 p51 * r 0 p50 * r state of port 5 pins note: * determined by the state of pins p57 to p50. port6?ort 6 register h'ff55 port 6 bit initial value read/write 7 0 6 0 5 p65 * r 4 p64 * r 3 p63 * r 2 p62 * r 1 p61 * r 0 p60 * r state of port 6 pins note: * determined by the state of pins p65 to p60.
563 port7?ort 7 register h'ff56 port 7 bit initial value read/write 7 0 6 0 5 p75 * r 4 p74 * r 3 p73 * r 2 p72 * r 1 p71 * r 0 p70 * r state of port 7 pins note: * determined by the state of pins p75 to p70. port8?ort 8 register h'ff57 port 8 bit initial value read/write 7 0 6 0 5 p85 * r 4 p84 * r 3 p83 * r 2 p82 * r 1 p81 * r 0 p80 * r state of port 8 pins note: * determined by the state of pins p85 to p80. porta?ort a register h'ff59 port a bit initial value read/write 7 pa7 * r 6 pa6 * r 5 pa5 * r 4 pa4 * r 3 pa3 * r 2 pa2 * r 1 pa1 * r 0 pa0 * r state of port a pins note: * determined by the state of pins pa7 to pa0.
564 portb?ort b register h'ff5a port b bit initial value read/write 7 pb7 * r 6 pb6 * r 5 pb5 * r 4 pb4 * r 3 pb3 * r 2 pb2 * r 1 pb1 * r 0 pb0 * r state of port b pins note: * determined by the state of pins pb7 to pb0. portc?ort c register h'ff5b port c bit initial value read/write 7 pc7 * r 6 pc6 * r 5 pc5 * r 4 pc4 * r 3 pc3 * r 2 pc2 * r 1 pc1 * r 0 pc0 * r state of port c pins note: * determined by the state of pins pc7 to pc0. portd?ort d register h'ff5c port d bit initial value read/write 7 pd7 * r 6 pd6 * r 5 pd5 * r 4 pd4 * r 3 pd3 * r 2 pd2 * r 1 pd1 * r 0 pd0 * r state of port d pins note: * determined by the state of pins pd7 to pd0.
565 porte?ort e register h'ff5d port e bit initial value read/write 7 pe7 * r 6 pe6 * r 5 pe5 * r 4 pe4 * r 3 pe3 * r 2 pe2 * r 1 pe1 * r 0 pe0 * r state of port e pins note: * determined by the state of pins pe7 to pe0. portf?ort f register h'ff5e port f bit initial value read/write 7 pf7 * r 6 pf6 * r 5 pf5 * r 4 pf4 * r 3 pf3 * r 2 pf2 * r 1 pf1 * r 0 pf0 * r state of port f pins note: * determined by the state of pins pf7 to pf0. portg?ort g register h'ff5f port g bit initial value read/write 7 undefined 6 pg6 * r 5 pg5 * r 4 pg4 * r 3 pg3 * r 2 pg2 * r 1 pg1 * r 0 pg0 * r state of port g pins note: * determined by the state of pins pg6 to pg0.
566 p1dr?ort 1 data register h'ff60 port 1 bit initial value read/write 7 p17dr 0 r/w 6 p16dr 0 r/w 5 p15dr 0 r/w 4 p14dr 0 r/w 3 p13dr 0 r/w 2 p12dr 0 r/w 1 p11dr 0 r/w 0 p10dr 0 r/w stores output data for port 1 pins (p17 to p10) p2dr?ort 2 data register h'ff61 port 2 bit initial value read/write 7 p27dr 0 r/w 6 p26dr 0 r/w 5 p25dr 0 r/w 4 p24dr 0 r/w 3 p23dr 0 r/w 2 p22dr 0 r/w 1 p21dr 0 r/w 0 p20dr 0 r/w stores output data for port 2 pins (p27 to p20) p3dr?ort 3 data register h'ff62 port 3 bit initial value read/write 7 0 6 0 5 p35dr 0 r/w 4 p34dr 0 r/w 3 p33dr 0 r/w 2 p32dr 0 r/w 1 p31dr 0 r/w 0 p30dr 0 r/w stores data for port 3 pins (p35 to p30) p5dr?ort 5 data register h'ff64 port 5 bit initial value read/write 7 0 6 0 5 0 4 0 3 p53dr 0 r/w 2 p52dr 0 r/w 1 p51dr 0 r/w 0 p50dr 0 r/w stores data for port 5 pins (p53 to p50)
567 p6dr?ort 6 data register h'ff65 port 6 bit initial value read/write 7 0 6 0 5 p65dr 0 r/w 4 p64dr 0 r/w 3 p63dr 0 r/w 2 p62dr 0 r/w 1 p61dr 0 r/w 0 p60dr 0 r/w stores output data for port 6 pins (p65 to p60) p7dr?ort 7 data register h'ff66 port 7 bit initial value read/write 7 0 6 0 5 p75dr 0 r/w 4 p74dr 0 r/w 3 p73dr 0 r/w 2 p72dr 0 r/w 1 p71dr 0 r/w 0 p70dr 0 r/w stores output data for port 7 pins (p75 to p70) p8dr?ort 8 data register h'ff67 port 8 bit initial value read/write 7 0 6 0 5 p85dr 0 r/w 4 p84dr 0 r/w 3 p83dr 0 r/w 2 p82dr 0 r/w 1 p81dr 0 r/w 0 p80dr 0 r/w stores output data for port 8 pins (p85 to p80) padr?ort a data register h'ff69 port a bit initial value read/write 7 pa7dr 0 r/w 6 pa6dr 0 r/w 5 pa5dr 0 r/w 4 pa4dr 0 r/w 3 pa3dr 0 r/w 2 pa2dr 0 r/w 1 pa1dr 0 r/w 0 pa0dr 0 r/w stores output data for port a pins (pa7 to pa0)
568 pbdr?ort b data register h'ff6a port b bit initial value read/write 7 pb7dr 0 r/w 6 pb6dr 0 r/w 5 pb5dr 0 r/w 4 pb4dr 0 r/w 3 pb3dr 0 r/w 2 pb2dr 0 r/w 1 pb1dr 0 r/w 0 pb0dr 0 r/w stores output data for port b pins (pb7 to pb0) pcdr?ort c data register h'ff6b port c bit initial value read/write 7 pc7dr 0 r/w 6 pc6dr 0 r/w 5 pc5dr 0 r/w 4 pc4dr 0 r/w 3 pc3dr 0 r/w 2 pc2dr 0 r/w 1 pc1dr 0 r/w 0 pc0dr 0 r/w stores output data for port c pins (pc7 to pc0) pddr?ort d data register h'ff6c port d bit initial value read/write 7 pd7dr 0 r/w 6 pd6dr 0 r/w 5 pd5dr 0 r/w 4 pd4dr 0 r/w 3 pd3dr 0 r/w 2 pd2dr 0 r/w 1 pd1dr 0 r/w 0 pd0dr 0 r/w stores output data for port d pins (pd7 to pd0) pedr?ort e data register h'ff6d port e bit initial value read/write 7 pe7dr 0 r/w 6 pe6dr 0 r/w 5 pe5dr 0 r/w 4 pe4dr 0 r/w 3 pe3dr 0 r/w 2 pe2dr 0 r/w 1 pe1dr 0 r/w 0 pe0dr 0 r/w stores output data for port e pins (pe7 to pe0)
569 pfdr?ort f data register h'ff6e port f bit initial value read/write 7 pf7dr 0 r/w 6 pf6dr 0 r/w 5 pf5dr 0 r/w 4 pf4dr 0 r/w 3 pf3dr 0 r/w 2 pf2dr 0 r/w 1 pf1dr 0 r/w 0 pf0dr 0 r/w stores output data for port f pins (pf7 to pf0) pgdr?ort g data register h'ff6f port g bit initial value read/write 7 0 6 pg6dr 0 r/w 5 pg5dr 0 r/w 4 pg4dr 0 r/w 3 pg3dr 0 r/w 2 pg2dr 0 r/w 1 pg1dr 0 r/w 0 pg0dr 0 r/w stores output data for port g pins (pg6 to pg0) porth?ort h register h'ff70 port h bit initial value read/write 7 undefined 6 undefined 5 undefined 4 undefined 3 ph3 * r 2 ph2 * r 1 ph1 * r 0 ph0 * r state of port h pins note: * determined by the state of pins ph3 to ph0. phdr?ort h data register h'ff72 port h bit initial value read/write 7 0 6 0 5 0 4 0 3 ph3dr 0 r/w 2 ph2dr 0 r/w 1 ph1dr 0 r/w 0 ph0dr 0 r/w stores output data for port h pins (ph3 to ph0)
570 phddr?ort h data direction register h'ff74 port h bit initial value read/write 7 0 6 0 5 0 4 0 3 ph3ddr 0 w 2 ph2ddr 0 w 1 ph1ddr 0 w 0 ph0ddr 0 w specify input or output for individual port h pins
571 smr0?erial mode register 0 h'ff78 sci0 bit initial value read/write 7 c/ a 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 stop 0 r/w 2 mp 0 r/w 1 cks1 0 r/w 0 cks0 0 r/w 0 0 clock /4 clock /16 clock /64 clock clock select 1 10 1 0 multiprocessor function disabled multiprocessor format selected multiprocessor mode 1 0 1 stop bit 2 stop bits stop bit length 1 0 even parity odd parity parity mode 1 0 parity bit addition and checking disabled parity bit addition and checking enabled parity enable 1 0 8-bit data 7-bit data * character length 1 0 asynchronous mode synchronous mode asynchronous mode/synchronous mode select 1 note: * when 7-bit data is selected, the msb (bit 7) of tdr is not transmitted, and lsb-first/ msb-first selection is not available.
572 smr0?erial mode register 0 h'ff78 smart card interface 0 bit initial value read/write 7 gm 0 r/w 6 blk 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 bcp1 0 r/w 2 bcp0 0 r/w 1 cks1 0 r/w 0 cks0 0 r/w 0 0 clock /4 clock /16 clock /64 clock clock select 1 10 1 0 even parity odd parity parity mode 1 0 setting prohibited parity bit addition and checking enabled parity enable (set to 1 when using smart card interface) 1 0 normal smart card interface mode block transfer mode block transfer mode select 1 0 normal smart card interface mode operation tend flag generation 12.5 etu after beginning of start bit (11.5 etu in block transfer mode) clock output on/off control only gsm mode smart card interface mode operation tend flag generation 11.0 etu after beginning of start bit high/low fixing control possible in addition to clock output on/off control (set by scr) gsm mode 1 note: etu (elementary time unit): time for transfer of 1 bit 0 0 bcp1 bcp0 basic clock pulse 32 clock periods 64 clock periods 372 clock periods 256 clock periods basic clock pulse 1 10 1
573 brr0?it rate register 0 h'ff79 sci0, smart card interface 0 bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w sets the serial transmit/receive bit rate note: for details see section 12.2.8, bit rate register (brr), in the h8s/2678 series hardware manual.
574 scr0?erial control register 0 h'ff7a sci0 bit initial value read/write 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 2 teie 0 r/w 1 cke1 0 r/w 0 cke0 0 r/w 0 asynchronous mode synchronous mode clock enable asynchronous mode synchronous mode asynchronous mode 1 synchronous mode asynchronous mode synchronous mode 0 0 1 1 internal clock/sck pin functions as i/o port internal clock/sck pin functions as serial clock output internal clock/sck pin functions as clock output * 1 internal clock/sck pin functions as serial clock output external clock/sck pin functions as clock input * 2 external clock/sck pin functions as serial clock input external clock/sck pin functions as clock input * 2 external clock/sck pin functions as serial clock input 0 transmit-end interrupt (tei) request disabled transmit-end interrupt (tei) request enabled transmit-end interrupt enable 1 0 reception disabled reception enabled receive enable 1 0 multiprocessor interrupts disabled [clearing conditions] when the mpie bit is cleared to 0 when data with mpb = 1 is received multiprocessor interrupts enabled receive interrupt (rxi) requests, receive-error interrupt (eri) requests, and setting of the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received multiprocessor interrupt enable 1 0 transmission disabled transmission enabled transmit enable 1 0 receive-data-full interrupt (rxi) request and receive-error interrupt (eri) request disabled receive-data-full interrupt (rxi) request and receive-error interrupt (eri) request enabled receive interrupt enable 1 0 transmit-data-empty interrupt (txi) request disabled transmit-data-empty interrupt (txi) request enabled transmit interrupt enable 1 notes: 1. outputs a clock of the same frequency as the bit rate. 2. inputs a clock with a frequency 16 times the bit rate.
575 scr0?erial control register 0 h'ff7a smart card interface 0 bit initial value read/write 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 2 teie 0 r/w 1 cke1 0 r/w 0 cke0 0 r/w scmr sck pin function see the sci specification clock enable (in smart card interface mode, with bit 7 of smr set to 1) smif 0 1 c/ a , gm 0 1 cke1 0 1 cke0 0 1 0 1 0 1 smr scr setting operates as port i/o pin outputs clock as sck output pin operates as sck output pin, with output fixed low outputs clock as sck output pin operates as sck output pin, with output fixed high outputs clock as sck output pin 0 transmit-end interrupt (tei) request disabled transmit-end interrupt (tei) request enabled transmit-end interrupt enable 1 0 multiprocessor interrupts disabled [clearing conditions] when the mpie bit is cleared to 0 when data with mpb = 1 is received multiprocessor interrupts enabled receive interrupt (rxi) requests, receive-error interrupt (eri) requests, and setting of the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received multiprocessor interrupt enable 1 0 reception disabled reception enabled receive enable 1 0 transmission disabled transmission enabled transmit enable 1 0 receive-data-full interrupt (rxi) request and receive-error interrupt (eri) request disabled receive-data-full interrupt (rxi) request and receive-error interrupt (eri) request enabled receive interrupt enable 1 0 transmit-data-empty interrupt (txi) request disabled transmit-data-empty interrupt (txi) request enabled transmit interrupt enable 1
576 tdr0?ransmit data register 0 h'ff7b sci0, smart card interface 0 bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w stores data for serial transmission
577 ssr0?erial status register 0 h'ff7c sci0 bit initial value read/write 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 fer 0 r/(w) * 3 per 0 r/(w) * 2 tend 1 r 1 mpb 0 r 0 mpbt 0 r/w 0 data with a 0 multiprocessor bit is transmitted data with a 1 multiprocessor bit is transmitted multiprocessor bit transfer 1 0 [clearing condition] when data with a 0 multiprocessor bit is received [setting condition] when data with a 1 multiprocessor bit is received multiprocessor bit 1 0 [clearing conditions] when 0 is written to tdre after reading tdre = 1 when the dmac or dtc is activated by a txi interrupt and writes data to tdr [setting conditions] when the te bit in scr is 0 when tdre = 1 at transmission of the last bit of a 1-byte serial transmit character transmit end 1 0 [clearing condition] when 0 is written to per after reading per = 1 [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/ e bit in smr parity error 1 0 [clearing condition] when 0 is written to fer after reading fer = 1 [setting condition] when the sci checks the stop bit at the end of the receive data when reception ends, and the stop bit is 0 framing error 1 0 [clearing condition] when 0 is written to orer after reading orer = 1 [setting condition] when the next serial reception is completed while rdrf = 1 overrun error 1 0 [clearing conditions] when 0 is written to rdrf after reading rdrf = 1 when the dmac or dtc is activated by an rxi interrupt and reads data from rdr [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr receive data register full 1 0 [clearing conditions] when 0 is written to tdre after reading tdre = 1 when the dmac or dtc is activated by a txi interrupt and writes data to tdr [setting conditions] when the te bit in scr is 0 when data is transferred from tdr to tsr and data can be written to tdr transmit data register empty 1 note: * can only be written with 0, to clear the flag.
578 ssr0?erial status register 0 h'ff7c smart card interface 0 bit initial value read/write 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 ers 0 r/(w) * 3 per 0 r/(w) * 2 tend 1 r 1 mpb 0 r 0 mpbt 0 r/w 0 multiprocessor bit transfer 1 0 multiprocessor bit 1 0 transmit end 1 0 transmit data register empty 1 note: * can only be written with 0, to clear the flag. 0 receive data register full 1 0 overrun error 1 0 error signal status 1 0 parity error 1 note: etu (elementary time unit): time for transfer of 1 bit data with a 0 multiprocessor bit is transmitted data with a 1 multiprocessor bit is transmitted [clearing condition] when data with a 0 multiprocessor bit is received [setting condition] when data with a 1 multiprocessor bit is received transmission is in progress [clearing conditions] when 0 is written to tdre after reading tdre = 1 when the dmac or dtc is activated by a txi interrupt and writes data to tdr [clearing condition] when 0 is written to per after reading per = 1 [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/ e bit in smr data received normally no error signal [clearing conditions] upon reset, and in standby mode or module stop mode when 0 is written to ers after reading ers = 1 error signal has been sent from receiving device, indicating parity error detection [setting condition] when the low level of the error signal is sampled [clearing condition] when 0 is written to orer after reading orer = 1 [setting condition] when the next serial reception is completed while rdrf = 1 [clearing conditions] when 0 is written to rdrf after reading rdrf = 1 when the dmac or dtc is activated by an rxi interrupt and reads data from rdr [clearing conditions] when 0 is written to tdre after reading tdre = 1 when the dmac or dtc is activated by a txi interrupt and writes data to tdr [setting conditions] when the te bit in scr is 0 when data is transferred from tdr to tsr and data can be written to tdr [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr note: clearing the te bit in scr to 0 does not affect the ers flag, which retains its previous state. transmission has ended [setting conditions] upon reset, and in standby mode or module stop mode when the te bit in scr is 0 and the ers bit is also 0 when tdre = 1 ers = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character when gm = 0 and blk = 0 when tdre = 1 ers = 0 (normal transmission) 1.5 etu after transmission of a 1-byte serial character when gm = 0 and blk = 1 when tdre = 1 ers = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when gm = 1 and blk = 0 when tdre = 1 ers = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when gm = 1 and blk = 1
579 rdr0?eceive data register 0 h'ff7d sci0, smart card interface 0 bit initial value read/write 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 2 0 r 1 0 r 0 0 r stores received serial data scmr0?mart card mode register 0 h'ff7e sci0, smart card interface 0 bit initial value read/write 7 1 6 1 5 1 4 1 3 sdir 0 r/w 2 sinv 0 r/w 1 1 0 smif 0 r/w 0 smart card interface mode select 1 0 data invert 1 0 data direction 1 smart card interface function is disabled smart card interface function is enabled tdr contents are transmitted as they are receive data is stored as it is in rdr tdr contents are inverted before being transmitted receive data is stored in inverted form in rdr tdr contents are transmitted lsb-first receive data is stored in rdr lsb-first tdr contents are transmitted msb-first receive data is stored in rdr msb-first
580 smr1?erial mode register 1 h'ff80 sci1 bit initial value read/write 7 c/ a 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 stop 0 r/w 2 mp 0 r/w 1 cks1 0 r/w 0 cks0 0 r/w 0 0 clock /4 clock /16 clock /64 clock clock select 1 10 1 0 multiprocessor function disabled multiprocessor format selected multiprocessor mode 1 0 1 stop bit 2 stop bits stop bit length 1 0 even parity odd parity parity mode 1 0 parity bit addition and checking disabled parity bit addition and checking enabled parity enable 1 0 8-bit data 7-bit data * character length 1 0 asynchronous mode synchronous mode asynchronous mode/synchronous mode select 1 note: * when 7-bit data is selected, the msb (bit 7) of tdr is not transmitted, and lsb-first/ msb-first selection is not available.
581 smr1?erial mode register 1 h'ff80 smart card interface 1 bit initial value read/write 7 gm 0 r/w 6 blk 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 bcp1 0 r/w 2 bcp0 0 r/w 1 cks1 0 r/w 0 cks0 0 r/w 0 0 clock /4 clock /16 clock /64 clock clock select 1 10 1 0 even parity odd parity parity mode 1 0 setting prohibited parity bit addition and checking enabled parity enable (set to 1 when using smart card interface) 1 0 normal smart card interface mode block transfer mode block transfer mode select 1 0 normal smart card interface mode operation tend flag generation 12.5 etu after beginning of start bit (11.5 etu in block transfer mode) clock output on/off control only gsm mode smart card interface mode operation tend flag generation 11.0 etu after beginning of start bit high/low fixing control possible in addition to clock output on/off control (set by scr) gsm mode 1 note: etu (elementary time unit): time for transfer of 1 bit 0 0 bcp1 bcp0 basic clock pulse 32 clock periods 64 clock periods 372 clock periods 256 clock periods basic clock pulse 1 10 1
582 brr1?it rate register 1 h'ff81 sci1, smart card interface 1 bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w sets the serial transmit/receive bit rate note: for details see section 12.2.8, bit rate register (brr), in the h8s/2678 series hardware manual.
583 scr1?erial control register 1 h'ff82 sci1 bit initial value read/write 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 2 teie 0 r/w 1 cke1 0 r/w 0 cke0 0 r/w 0 asynchronous mode synchronous mode clock enable asynchronous mode synchronous mode asynchronous mode 1 synchronous mode asynchronous mode synchronous mode 0 0 1 1 internal clock/sck pin functions as i/o port internal clock/sck pin functions as serial clock output internal clock/sck pin functions as clock output * 1 internal clock/sck pin functions as serial clock output external clock/sck pin functions as clock input * 2 external clock/sck pin functions as serial clock input external clock/sck pin functions as clock input * 2 external clock/sck pin functions as serial clock input 0 transmit-end interrupt (tei) request disabled transmit-end interrupt (tei) request enabled transmit-end interrupt enable 1 0 reception disabled reception enabled receive enable 1 0 multiprocessor interrupts disabled [clearing conditions] when the mpie bit is cleared to 0 when data with mpb = 1 is received multiprocessor interrupts enabled receive interrupt (rxi) requests, receive-error interrupt (eri) requests, and setting of the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received multiprocessor interrupt enable 1 0 transmission disabled transmission enabled transmit enable 1 0 receive-data-full interrupt (rxi) request and receive-error interrupt (eri) request disabled receive-data-full interrupt (rxi) request and receive-error interrupt (eri) request enabled receive interrupt enable 1 0 transmit-data-empty interrupt (txi) request disabled transmit-data-empty interrupt (txi) request enabled transmit interrupt enable 1 notes: 1. outputs a clock of the same frequency as the bit rate. 2. inputs a clock with a frequency 16 times the bit rate.
584 scr1?erial control register 1 h'ff82 smart card interface 1 bit initial value read/write 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 2 teie 0 r/w 1 cke1 0 r/w 0 cke0 0 r/w scmr sck pin function see the sci specification clock enable (in smart card interface mode, with bit 7 of smr set to 1) smif 0 1 c/ a , gm 0 1 cke1 0 1 cke0 0 1 0 1 0 1 smr scr setting operates as port i/o pin outputs clock as sck output pin operates as sck output pin, with output fixed low outputs clock as sck output pin operates as sck output pin, with output fixed high outputs clock as sck output pin 0 transmit-end interrupt (tei) request disabled transmit-end interrupt (tei) request enabled transmit-end interrupt enable 1 0 multiprocessor interrupts disabled [clearing conditions] when the mpie bit is cleared to 0 when data with mpb = 1 is received multiprocessor interrupts enabled receive interrupt (rxi) requests, receive-error interrupt (eri) requests, and setting of the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received multiprocessor interrupt enable 1 0 reception disabled reception enabled receive enable 1 0 transmission disabled transmission enabled transmit enable 1 0 receive-data-full interrupt (rxi) request and receive-error interrupt (eri) request disabled receive-data-full interrupt (rxi) request and receive-error interrupt (eri) request enabled receive interrupt enable 1 0 transmit-data-empty interrupt (txi) request disabled transmit-data-empty interrupt (txi) request enabled transmit interrupt enable 1
585 tdr1?ransmit data register 1 h'ff83 sci1, smart card interface 1 bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w stores data for serial transmission
586 ssr1?erial status register 1 h'ff84 sci1 bit initial value read/write 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 fer 0 r/(w) * 3 per 0 r/(w) * 2 tend 1 r 1 mpb 0 r 0 mpbt 0 r/w 0 data with a 0 multiprocessor bit is transmitted data with a 1 multiprocessor bit is transmitted multiprocessor bit transfer 1 0 [clearing condition] when data with a 0 multiprocessor bit is received [setting condition] when data with a 1 multiprocessor bit is received multiprocessor bit 1 0 [clearing conditions] when 0 is written to tdre after reading tdre = 1 when the dmac or dtc is activated by a txi interrupt and writes data to tdr [setting conditions] when the te bit in scr is 0 when tdre = 1 at transmission of the last bit of a 1-byte serial transmit character transmit end 1 0 [clearing condition] when 0 is written to per after reading per = 1 [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/ e bit in smr parity error 1 0 [clearing condition] when 0 is written to fer after reading fer = 1 [setting condition] when the sci checks the stop bit at the end of the receive data when reception ends, and the stop bit is 0 framing error 1 0 [clearing condition] when 0 is written to orer after reading orer = 1 [setting condition] when the next serial reception is completed while rdrf = 1 overrun error 1 0 [clearing conditions] when 0 is written to rdrf after reading rdrf = 1 when the dmac or dtc is activated by an rxi interrupt and reads data from rdr [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr receive data register full 1 0 [clearing conditions] when 0 is written to tdre after reading tdre = 1 when the dmac or dtc is activated by a txi interrupt and writes data to tdr [setting conditions] when the te bit in scr is 0 when data is transferred from tdr to tsr and data can be written to tdr transmit data register empty 1 note: * can only be written with 0, to clear the flag.
587 ssr1?erial status register 1 h'ff84 smart card interface 1 bit initial value read/write 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 ers 0 r/(w) * 3 per 0 r/(w) * 2 tend 1 r 1 mpb 0 r 0 mpbt 0 r/w 0 multiprocessor bit transfer 1 0 multiprocessor bit 1 0 transmit end 1 0 transmit data register empty 1 note: * can only be written with 0, to clear the flag. 0 receive data register full 1 0 overrun error 1 0 error signal status 1 0 parity error 1 note: etu (elementary time unit): time for transfer of 1 bit data with a 0 multiprocessor bit is transmitted data with a 1 multiprocessor bit is transmitted [clearing condition] when data with a 0 multiprocessor bit is received [setting condition] when data with a 1 multiprocessor bit is received transmission is in progress [clearing conditions] when 0 is written to tdre after reading tdre = 1 when the dmac or dtc is activated by a txi interrupt and writes data to tdr [clearing condition] when 0 is written to per after reading per = 1 [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/ e bit in smr data received normally no error signal [clearing conditions] upon reset, and in standby mode or module stop mode when 0 is written to ers after reading ers = 1 error signal has been sent from receiving device, indicating parity error detection [setting condition] when the low level of the error signal is sampled [clearing condition] when 0 is written to orer after reading orer = 1 [setting condition] when the next serial reception is completed while rdrf = 1 [clearing conditions] when 0 is written to rdrf after reading rdrf = 1 when the dmac or dtc is activated by an rxi interrupt and reads data from rdr [clearing conditions] when 0 is written to tdre after reading tdre = 1 when the dmac or dtc is activated by a txi interrupt and writes data to tdr [setting conditions] when the te bit in scr is 0 when data is transferred from tdr to tsr and data can be written to tdr [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr note: clearing the te bit in scr to 0 does not affect the ers flag, which retains its previous state. transmission has ended [setting conditions] upon reset, and in standby mode or module stop mode when the te bit in scr is 0 and the ers bit is also 0 when tdre = 1 ers = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character when gm = 0 and blk = 0 when tdre = 1 ers = 0 (normal transmission) 1.5 etu after transmission of a 1-byte serial character when gm = 0 and blk = 1 when tdre = 1 ers = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when gm = 1 and blk = 0 when tdre = 1 ers = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when gm = 1 and blk = 1
588 rdr1?eceive data register 1 h'ff85 sci1, smart card interface 1 bit initial value read/write 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 2 0 r 1 0 r 0 0 r stores received serial data scmr1?mart card mode register 1 h'ff86 sci1, smart card interface 1 bit initial value read/write 7 1 6 1 5 1 4 1 3 sdir 0 r/w 2 sinv 0 r/w 1 1 0 smif 0 r/w 0 smart card interface mode select 1 0 data invert 1 0 data direction 1 smart card interface function is disabled smart card interface function is enabled tdr contents are transmitted as they are receive data is stored as it is in rdr tdr contents are inverted before being transmitted receive data is stored in inverted form in rdr tdr contents are transmitted lsb-first receive data is stored in rdr lsb-first tdr contents are transmitted msb-first receive data is stored in rdr msb-first
589 smr2?erial mode register 2 h'ff88 sci2 bit initial value read/write 7 c/ a 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 stop 0 r/w 2 mp 0 r/w 1 cks1 0 r/w 0 cks0 0 r/w 0 0 clock /4 clock /16 clock /64 clock clock select 1 10 1 0 multiprocessor function disabled multiprocessor format selected multiprocessor mode 1 0 1 stop bit 2 stop bits stop bit length 1 0 even parity odd parity parity mode 1 0 parity bit addition and checking disabled parity bit addition and checking enabled parity enable 1 0 8-bit data 7-bit data * character length 1 0 asynchronous mode synchronous mode asynchronous mode/synchronous mode select 1 note: * when 7-bit data is selected, the msb (bit 7) of tdr is not transmitted, and lsb-first/ msb-first selection is not available.
590 smr2?erial mode register 2 h'ff88 smart card interface 2 bit initial value read/write 7 gm 0 r/w 6 blk 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 bcp1 0 r/w 2 bcp0 0 r/w 1 cks1 0 r/w 0 cks0 0 r/w 0 0 clock /4 clock /16 clock /64 clock clock select 1 10 1 0 even parity odd parity parity mode 1 0 setting prohibited parity bit addition and checking enabled parity enable (set to 1 when using smart card interface) 1 0 normal smart card interface mode block transfer mode block transfer mode select 1 0 normal smart card interface mode operation tend flag generation 12.5 etu after beginning of start bit (11.5 etu in block transfer mode) clock output on/off control only gsm mode smart card interface mode operation tend flag generation 11.0 etu after beginning of start bit high/low fixing control possible in addition to clock output on/off control (set by scr) gsm mode 1 note: etu (elementary time unit): time for transfer of 1 bit 0 0 bcp1 bcp0 basic clock pulse 32 clock periods 64 clock periods 372 clock periods 256 clock periods basic clock pulse 1 10 1
591 brr2?it rate register 2 h'ff89 sci2, smart card interface 2 bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w sets the serial transmit/receive bit rate note: for details see section 12.2.8, bit rate register (brr), in the h8s/2678 series hardware manual.
592 scr2?erial control register 2 h'ff8a sci2 bit initial value read/write 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 2 teie 0 r/w 1 cke1 0 r/w 0 cke0 0 r/w 0 asynchronous mode synchronous mode clock enable asynchronous mode synchronous mode asynchronous mode 1 synchronous mode asynchronous mode synchronous mode 0 0 1 1 internal clock/sck pin functions as i/o port internal clock/sck pin functions as serial clock output internal clock/sck pin functions as clock output * 1 internal clock/sck pin functions as serial clock output external clock/sck pin functions as clock input * 2 external clock/sck pin functions as serial clock input external clock/sck pin functions as clock input * 2 external clock/sck pin functions as serial clock input 0 transmit-end interrupt (tei) request disabled transmit-end interrupt (tei) request enabled transmit-end interrupt enable 1 0 reception disabled reception enabled receive enable 1 0 multiprocessor interrupts disabled [clearing conditions] when the mpie bit is cleared to 0 when data with mpb = 1 is received multiprocessor interrupts enabled receive interrupt (rxi) requests, receive-error interrupt (eri) requests, and setting of the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received multiprocessor interrupt enable 1 0 transmission disabled transmission enabled transmit enable 1 0 receive-data-full interrupt (rxi) request and receive-error interrupt (eri) request disabled receive-data-full interrupt (rxi) request and receive-error interrupt (eri) request enabled receive interrupt enable 1 0 transmit-data-empty interrupt (txi) request disabled transmit-data-empty interrupt (txi) request enabled transmit interrupt enable 1 notes: 1. outputs a clock of the same frequency as the bit rate. 2. inputs a clock with a frequency 16 times the bit rate.
593 scr2?erial control register 2 h'ff8a smart card interface 2 bit initial value read/write 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 2 teie 0 r/w 1 cke1 0 r/w 0 cke0 0 r/w scmr sck pin function see the sci specification clock enable (in smart card interface mode, with bit 7 of smr set to 1) smif 0 1 c/ a , gm 0 1 cke1 0 1 cke0 0 1 0 1 0 1 smr scr setting operates as port i/o pin outputs clock as sck output pin operates as sck output pin, with output fixed low outputs clock as sck output pin operates as sck output pin, with output fixed high outputs clock as sck output pin 0 transmit-end interrupt (tei) request disabled transmit-end interrupt (tei) request enabled transmit-end interrupt enable 1 0 multiprocessor interrupts disabled [clearing conditions] when the mpie bit is cleared to 0 when data with mpb = 1 is received multiprocessor interrupts enabled receive interrupt (rxi) requests, receive-error interrupt (eri) requests, and setting of the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received multiprocessor interrupt enable 1 0 reception disabled reception enabled receive enable 1 0 transmission disabled transmission enabled transmit enable 1 0 receive-data-full interrupt (rxi) request and receive-error interrupt (eri) request disabled receive-data-full interrupt (rxi) request and receive-error interrupt (eri) request enabled receive interrupt enable 1 0 transmit-data-empty interrupt (txi) request disabled transmit-data-empty interrupt (txi) request enabled transmit interrupt enable 1
594 tdr2?ransmit data register 2 h'ff8b sci2, smart card interface 2 bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w stores data for serial transmission
595 ssr2?erial status register 2 h'ff8c sci2 bit initial value read/write 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 fer 0 r/(w) * 3 per 0 r/(w) * 2 tend 1 r 1 mpb 0 r 0 mpbt 0 r/w 0 data with a 0 multiprocessor bit is transmitted data with a 1 multiprocessor bit is transmitted multiprocessor bit transfer 1 0 [clearing condition] when data with a 0 multiprocessor bit is received [setting condition] when data with a 1 multiprocessor bit is received multiprocessor bit 1 0 [clearing conditions] when 0 is written to tdre after reading tdre = 1 when the dmac or dtc is activated by a txi interrupt and writes data to tdr [setting conditions] when the te bit in scr is 0 when tdre = 1 at transmission of the last bit of a 1-byte serial transmit character transmit end 1 0 [clearing condition] when 0 is written to per after reading per = 1 [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/ e bit in smr parity error 1 0 [clearing condition] when 0 is written to fer after reading fer = 1 [setting condition] when the sci checks the stop bit at the end of the receive data when reception ends, and the stop bit is 0 framing error 1 0 [clearing condition] when 0 is written to orer after reading orer = 1 [setting condition] when the next serial reception is completed while rdrf = 1 overrun error 1 0 [clearing conditions] when 0 is written to rdrf after reading rdrf = 1 when the dmac or dtc is activated by an rxi interrupt and reads data from rdr [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr receive data register full 1 0 [clearing conditions] when 0 is written to tdre after reading tdre = 1 when the dmac or dtc is activated by a txi interrupt and writes data to tdr [setting conditions] when the te bit in scr is 0 when data is transferred from tdr to tsr and data can be written to tdr transmit data register empty 1 note: * can only be written with 0, to clear the flag.
596 ssr2?erial status register 2 h'ff8c smart card interface 2 bit initial value read/write 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 ers 0 r/(w) * 3 per 0 r/(w) * 2 tend 1 r 1 mpb 0 r 0 mpbt 0 r/w 0 multiprocessor bit transfer 1 0 multiprocessor bit 1 0 transmit end 1 0 transmit data register empty 1 note: * can only be written with 0, to clear the flag. 0 receive data register full 1 0 overrun error 1 0 error signal status 1 0 parity error 1 note: etu (elementary time unit): time for transfer of 1 bit data with a 0 multiprocessor bit is transmitted data with a 1 multiprocessor bit is transmitted [clearing condition] when data with a 0 multiprocessor bit is received [setting condition] when data with a 1 multiprocessor bit is received transmission is in progress [clearing conditions] when 0 is written to tdre after reading tdre = 1 when the dmac or dtc is activated by a txi interrupt and writes data to tdr [clearing condition] when 0 is written to per after reading per = 1 [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/ e bit in smr data received normally no error signal [clearing conditions] upon reset, and in standby mode or module stop mode when 0 is written to ers after reading ers = 1 error signal has been sent from receiving device, indicating parity error detection [setting condition] when the low level of the error signal is sampled [clearing condition] when 0 is written to orer after reading orer = 1 [setting condition] when the next serial reception is completed while rdrf = 1 [clearing conditions] when 0 is written to rdrf after reading rdrf = 1 when the dmac or dtc is activated by an rxi interrupt and reads data from rdr [clearing conditions] when 0 is written to tdre after reading tdre = 1 when the dmac or dtc is activated by a txi interrupt and writes data to tdr [setting conditions] when the te bit in scr is 0 when data is transferred from tdr to tsr and data can be written to tdr [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr note: clearing the te bit in scr to 0 does not affect the ers flag, which retains its previous state. transmission has ended [setting conditions] upon reset, and in standby mode or module stop mode when the te bit in scr is 0 and the ers bit is also 0 when tdre = 1 ers = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character when gm = 0 and blk = 0 when tdre = 1 ers = 0 (normal transmission) 1.5 etu after transmission of a 1-byte serial character when gm = 0 and blk = 1 when tdre = 1 ers = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when gm = 1 and blk = 0 when tdre = 1 ers = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when gm = 1 and blk = 1
597 rdr2?eceive data register 2 h'ff8d sci2, smart card interface 2 bit initial value read/write 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 2 0 r 1 0 r 0 0 r stores received serial data scmr2?mart card mode register 2 h'ff8e sci2, smart card interface 2 bit initial value read/write 7 1 6 1 5 1 4 1 3 sdir 0 r/w 2 sinv 0 r/w 1 1 0 smif 0 r/w 0 smart card interface mode select 1 0 data invert 1 0 data direction 1 smart card interface function is disabled smart card interface function is enabled tdr contents are transmitted as they are receive data is stored as it is in rdr tdr contents are inverted before being transmitted receive data is stored in inverted form in rdr tdr contents are transmitted lsb-first receive data is stored in rdr lsb-first tdr contents are transmitted msb-first receive data is stored in rdr msb-first
598 addrah?/d data register ah h'ff90 a/d converter addral?/d data register al h'ff91 a/d converter addrbh?/d data register bh h'ff92 a/d converter addrbl?/d data register bl h'ff93 a/d converter addrch?/d data register ch h'ff94 a/d converter addrcl?/d data register cl h'ff95 a/d converter addrdh?/d data register dh h'ff96 a/d converter addrdl?/d data register dl h'ff97 a/d converter bit initial value read/write 15 ad9 0 r 14 ad8 0 r 13 ad7 0 r 12 ad6 0 r 11 ad5 0 r 10 ad4 0 r 9 ad3 0 r 8 ad2 0 r 7 ad1 0 r 6 ad0 0 r 5 0 r 4 0 r 3 0 r 2 0 r 1 0 r 0 0 r analog input channel a/d data register addra addrb addrc addrd stores the result of a/d conversion group 0 an0 an1 an2 an3 channel set 0 (ch3 = 1) channel set 1 (ch3 = 0) group 1 an4 an5 an6 an7 group 0 setting prohibited setting prohibited setting prohibited setting prohibited group 1 an12 an13 an14 an15
599 adcsr?/d control/status register h'ff98 a/d converter bit initial value read/write 7 adf 0 r/w * 6 adie 0 r/w 5 adst 0 r/w 4 scan 0 r/w 3 cks 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w 0 ch0 0 r/w channel select note: ch2, ch1, and ch0 are used in combination with bit 2 (ch3) in adcr. see adcr a/d control register (h'ff99) for details. clock select note: cks is used in combination with bit 3 (cks1) in adcr. see adcr a/d control register (h'ff99) for details. scan mode 0 single mode 1 scan mode a/d start 0 a/d conversion stopped 1 single mode: a/d conversion is started; cleared to 0 automatically when conversion ends scan mode: a/d conversion is started, and continues consecutively on the selected channels until adst is cleared to 0 by software, a reset, or a transition to standby mode or module stop mode a/d end flag 0 [clearing conditions] when 0 is written to adf after reading adf = 1 when the dtc is activated by an adf interrupt and addr is read 1 [setting conditions] single mode: when a/d conversion ends scan mode: when a/d conversion ends on all specified channels a/d interrupt enable 0 a/d conversion end interrupt request disabled 1 a/d conversion end interrupt request enabled note: * can only be written with 0, to clear the flag.
600 adcr?/d control register h'ff99 a/d converter bit initial value read/write 7 trgs1 0 r/w 6 trgs0 0 r/w 5 1 4 1 3 cks1 1 r/w 2 ch3 1 r/w 1 1 0 1 ch3 channel select selects the analog input channel(s). make the input channel setting when conversion is halted (adst = 0). ch2 * ch1 * ch0 * setting prohibited setting prohibited setting prohibited setting prohibited an12 an13 an14 an15 an0 (initial value) an1 an2 an3 an4 an5 an6 an7 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 setting prohibited setting prohibited setting prohibited setting prohibited an12 an12, an13 an12 to an14 an12 to an15 an0 an0, an1 an0 to an2 an0 to an3 an4 an4, an5 an4 to an6 an4 to an7 single mode description channel selection scan mode bit 3 description conversion time = 530 states (max.) conversion time = 68 states (max.) conversion time = 266 states (max.) (initial value) conversion time = 134 states (max.) a/d conversion start by external trigger is disabled a/d conversion start by external trigger (tpu) is enabled a/d conversion start by external trigger (8-bit timer) is enabled a/d conversion start by external trigger pin ( adtrg ) is enabled clock select cks1 0 1 adcsr bit 3 cks 0 1 0 1 timer trigger select trgs1 0 1 trgs0 0 1 0 1 description note: * ch2, ch1, and ch0 are bits in adcsr.
601 dadr0?/a data register 0 h'ffa4 d/a converter dadr1?/a data register 1 h'ffa5 d/a converter 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit initial value read/write stores data for d/a conversion dacr01?/a control register 01 h'ffa6 d/a converter 7 daoe1 0 r/w 6 daoe0 0 r/w 5 dae 0 r/w 4 1 3 1 0 1 2 1 1 1 bit initial value read/write * : don t care d/a output enable 0 0 da0 analog output disabled 1 channel 0 d/a conversion enabled. da0 analog output enabled d/a output enable 1 0 da1 analog output disabled 1 channel 1 d/a conversion enabled. da1 analog output enabled d/a conversion control 0 channel 0 and 1 d/a conversion disabled daoe0 description 1 channel 0 d/a conversion enabled * dae 0 0 daoe1 channel 1 d/a conversion disabled channel 0 and 1 d/a conversion enabled 1 0 channel 0 d/a conversion disabled 0 1 channel 1 d/a conversion enabled channel 0 and 1 d/a conversion enabled 1 1 channel 0 and 1 d/a conversion enabled *
602 dadr2?/a data register 2 h'ffa8 d/a converter dadr3?/a data register 3 h'ffa9 d/a converter 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit initial value read/write stores data for d/a conversion dacr23?/a control register 23 h'ffaa d/a converter 7 daoe1 0 r/w 6 daoe0 0 r/w 5 dae 0 r/w 4 1 3 1 0 1 2 1 1 1 bit initial value read/write * : don t care d/a output enable 0 0 da2 analog output disabled 1 channel 2 d/a conversion enabled. da2 analog output enabled d/a output enable 1 0 da3 analog output disabled 1 channel 3 d/a conversion enabled. da3 analog output enabled d/a conversion control 0 channel 2 and 3 d/a conversion disabled daoe description 1 channel 2 d/a conversion enabled * dae 0 0 daoe1 channel 3 d/a conversion disabled channel 2 and 3 d/a conversion enabled 1 0 channel 2 d/a conversion disabled 0 1 channel 3 d/a conversion enabled channel 2 and 3 d/a conversion enabled 1 1 channel 2 and 3 d/a conversion enabled *
603 tcr0?imer control register 0 h'ffb0 8-bit timer channel 0 tcr1?imer control register 1 h'ffb1 8-bit timer channel 1 bit initial value read/write 7 cmieb 0 r/w 6 cmiea 0 r/w 5 ovie 0 r/w 4 cclr1 0 r/w 3 cclr0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w 0 cks0 0 r/w clock select 0 clock input disabled 1 0 1 internal clock: count at falling edge of /8 internal clock: count at falling edge of /64 internal clock: count at falling edge of /8192 for channel 0: count at tcnt1 overflow signal * for channel 1: count at tcnt0 compare match a external clock: count at rising edge 0 1 0 1 00 1 external clock: count at falling edge 10 external clock: count at both rising and falling edges 1 note: * if the clock input of channel 0 is the tcnt1 overflow signal and that of channel 1 is the tcnt0 compare match signal, no incrementing clock is generated. do not use this setting. counter clear 0 clearing is disabled 1 0 1 0 1 clear by compare match a clear by compare match b clear by rising edge of external reset input timer overflow interrupt enable 0 ovf interrupt request (ovi) is disabled 1 ovf interrupt request (ovi) is enabled compare match interrupt enable a 0 cmfa interrupt request (cmia) is disabled 1 cmfa interrupt request (cmia) is enabled compare match interrupt enable b 0 cmfb interrupt request (cmib) is disabled 1 cmfb interrupt request (cmib) is enabled
604 tcsr0?imer control/status register 0 h'ffb2 8-bit timer channel 0 tcsr1?imer control/status register 1 h'ffb3 8-bit timer channel 1 bit initial value read/write tcsr0 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 adte 0 r/w 3 os3 0 r/w 2 os2 0 r/w 1 os1 0 r/w 0 os0 0 r/w bit initial value read/write tcsr1 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 1 3 os3 0 r/w 2 os2 0 r/w 1 os1 0 r/w 0 os0 0 r/w output select 0 no change when compare match a occurs 1 0 1 0 1 0 is output when compare match a occurs 1 is output when compare match a occurs output is inverted when compare match a occurs (toggle output) output select 0 no change when compare match b occurs 1 0 1 0 1 0 is output when compare match b occurs 1 is output when compare match b occurs output is inverted when compare match b occurs (toggle output) a/d trigger enable (tcsr0 only) 0 a/d converter start requests by compare match a are disabled 1 a/d converter start requests by compare match a are enabled timer overflow flag 0 [clearing condition] when 0 is written to ovf after reading ovf = 1 1 [setting condition] when tcnt overflows (from h'ff to h'00) compare match flag a 0 [clearing conditions] when 0 is written to cmfa after reading cmfa = 1 when the dtc is activated by a cmia interrupt, and the disel bit in the dtc s mrb register is 0 1 [setting condition] when tcnt = tcora compare match flag b 0 [clearing conditions] when 0 is written to cmfb after reading cmfb = 1 when the dtc is activated by a cmib interrupt, and the disel bit in the dtc s mrb register is 0 1 [setting condition] when tcnt = tcorb note: * only 0 can be written to bits 7 to 5, to clear the flags.
605 tcora0?ime constant register a0 h'ffb4 8-bit timer channel 0 tcora1?ime constant register a1 h'ffb5 8-bit timer channel 1 bit initial value read/write 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w tcora0 tcora1 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w tcorb0?ime constant register b0 h'ffb6 8-bit timer channel 0 tcorb1?ime constant register b1 h'ffb7 8-bit timer channel 1 bit initial value read/write 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w tcorb0 tcorb1 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w tcnt0?imer counter 0 h'ffb8 8-bit timer channel 0 tcnt1?imer counter 1 h'ffb9 8-bit timer channel 1 bit initial value read/write 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w tcnt0 tcnt1 11 0 r/w 10 0 r/w 9 0 r/w 8 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w
606 tcsr?imer control/status register h'ffbc (w) h'ffbc (r) wdt bit initial value read/write 7 ovf 0 r/(w) * 1 6 wt/ it 0 r/w 5 tme 0 r/w 4 1 3 1 2 cks2 0 r/w 1 cks1 0 r/w 0 cks0 0 r/w cks2 clock select 0 1 clock /2 (initial value) /64 /128 /512 /2048 /8192 /32768 /131072 cks1 0 1 0 1 cks0 0 1 0 1 0 1 0 1 overflow period * (when = 20 mhz) 25.6 s 819.2 s 1.6 ms 6.6 ms 26.2 ms 104.9 ms 419.4 ms 1.68 s 0 tcnt is initialized to h'00 and halted tcnt counts timer enable 1 note: * the overflow period is the time from when tcnt starts counting up from h'00 until overflow occurs. 0 interval timer mode: sends the cpu an interval timer interrupt request (wovi) when tcnt overflows watchdog timer mode: outputs the wdtovf signal * 2 externally when tcnt overflows timer mode select 1 0 [clearing condition] when 0 is written to ovf after reading tcsr when ovf = 1 [setting condition] when tcnt overflows (from h'ff to h'00) in interval timer mode. when internal reset requests are selected in watchdog timer mode, however, after being set ovf is cleared automatically by an internal reset. overflow flag 1 the method for writing to tcsr is different from that for general registers to prevent accidental overwriting. for details see section 11.2.4, notes on register access, in the h8s/2678 series hardware manual. notes: 1. can only be written with 0, to clear the flag. 2. the wdtovf function is not available in the f-ztat version.
607 tcnt?imer counter h'ffbc (w) h'ffbd (r) wdt bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w rstcsr?eset control/status register h'ffbe (w) h'ffbf (r) wdt bit initial value read/write 7 wovf 0 r/(w) * 6 rste 0 r/w 5 0 r/w 4 1 3 1 2 1 1 1 0 1 reserved bit writes to this bit are invalid. 0 internal reset is not performed when tcnt overflows * internal reset is performed when tcnt overflows reset enable 1 note: * the chip is not initialized internally, but the tcnt and tcsr registers in the wdt are reset. 0 [clearing condition] when 0 is written to wovf after reading tcsr when wovf = 1 [setting condition] when tcnt overflows (from h'ff to h'00) in watchdog timer mode watchdog overflow flag 1 notes: * can only be written with 0, to clear the flag. the method for writing to rstcsr is different from that for general registers to prevent accidental overwriting. for details see section 11.2.4, notes on register access, in the h8s/2678 series hardware manual.
608 tstr?imer start register h'ffc0 tpu bit initial value read/write 7 0 6 0 5 cst5 0 r/w 4 cst4 0 r/w 3 cst3 0 r/w 2 cst2 0 r/w 1 cst1 0 r/w 0 cst0 0 r/w 0 tcntn count operation is stopped tcntn performs count operation counter start 1 (n = 5 to 0) note: if 0 is written to the cst bit during operation with the tioc pin designated for output, the counter stops but the tioc pin output compare output level is retained. if tior is written to when the cst bit is cleared to 0, the pin output level will be changed to the set initial output value. tsyr?imer sync register h'ffc1 tpu bit initial value read/write 7 0 6 0 5 sync5 0 r/w 4 sync4 0 r/w 3 sync3 0 r/w 2 sync2 0 r/w 1 sync1 0 r/w 0 sync0 0 r/w 0 tcntn operates independently (tcnt presetting/clearing is unrelated to other channels) tcntn performs synchronous operation tcnt synchronous presetting * 1 /synchronous clearing * 2 is possible timer synchronization 1 (n = 5 to 0) notes: 1. to set synchronous operation, the sync bits for at least two channels must be set to 1. 2. to set synchronous clearing, in addition to the sync bit , the tcnt clearing source must also be set by means of bits cclr2 to cclr0 in tcr.
609 flmcr1?lash memory control register 1 h'ffc8 flash memory (f-ztat version only) bit initial value read/write 7 fwe 1/0 r 6 swe 0 r/w 5 esu 0 r/w 4 psu 0 r/w 3 ev 0 r/w 2 pv 0 r/w 1 e 0 r/w 0 p 0 r/w 0 program mode cleared transition to program mode [setting condition] when fwe = 1, swe = 1, and psu = 1 program 1 0 erase mode cleared transition to erase mode [setting condition] when fwe = 1, swe = 1, and esu = 1 erase 1 0 program-verify mode cleared transition to program-verify mode [setting condition] when fwe = 1 and swe = 1 program-verify 1 0 erase-verify mode cleared transition to erase-verify mode [setting condition] when fwe = 1 and swe = 1 erase-verify 1 0 program setup cleared program setup [setting condition] when fwe = 1 and swe = 1 program setup 1 0 erase setup cleared erase setup [setting condition] when fwe = 1 and swe = 1 erase setup 1 0 writes disabled writes enabled [setting condition] when fwe = 1 software write enable 1 0 when a low level is input to the fwe pin (hardware-protected state) when a high level is input to the fwe pin flash write enable 1 note: determined by the state of fwe pin.
610 flmcr2?lash memory control register 2 h'ffc9 flash memory (f-ztat version only) ?preliminary bit initial value read/write 7 fler 0 r 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w 0 flash memory is operating normally flash memory program/erase protection (error protection) is disabled [clearing condition] power on reset or hardware standby mode an error has occurred during flash memory programming/erasing flash memory program/erase protection (error protection) is enabled [setting condition] see section 18.10.3, error protection, in the h8s/2678 series hardware manual. flash memory error 1 ebr1?rase block register 1 h'ffca flash memory ebr2?rase block register 2 h'ffcb flash memory (f-ztat version only) ?preliminary bit ebr1 initial value read/write 7 eb7 0 r/w 6 eb6 0 r/w 5 eb5 0 r/w 4 eb4 0 r/w 3 eb3 0 r/w 2 eb2 0 r/w 1 eb1 0 r/w 0 eb0 0 r/w bit ebr2 initial value read/write 7 0 6 0 5 0 4 0 3 eb11 0 r/w 2 eb10 0 r/w 1 eb9 0 r/w 0 eb8 0 r/w
611 tcr0?imer control register 0 h'ffd0 tpu0 bit initial value read/write 7 cclr2 0 r/w 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w 0 tpsc0 0 r/w 0 1 0 1 0 1 internal clock: count on /1 internal clock: count on /4 internal clock: count on /16 internal clock: count on /64 external clock: count on tclka pin input external clock: count on tclkb pin input external clock: count on tclkc pin input external clock: count on tclkd pin input time prescaler 0 1 0 1 0 1 0 1 0 1 0 1 count at rising edge count at falling edge count at both edges input clock edge select 0 0 tcnt clearing disabled tcnt cleared by tgra compare match/input capture tcnt cleared by tgrb compare match/input capture counter clear 0 1 10 1 100 1 10 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * 1 tcnt clearing disabled tcnt cleared by tgrc compare match/input capture * 2 tcnt cleared by tgrd compare match/input capture * 2 tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * 1 notes: 1. synchronous operation is selected by setting the sync bit in tsyr to 1. 2. when tgrc or tgrd is used as a buffer register, tcnt is not cleared because the buffer register setting has priority, and compare match/input capture does not occur.
612 tmdr0?imer mode register 0 h'ffd1 tpu0 bit initial value read/write 7 1 6 1 5 bfb 0 r/w 4 bfa 0 r/w 3 md3 0 r/w 2 md2 0 r/w 1 md1 0 r/w 0 md0 0 r/w 0 0 normal operation reserved pwm mode 1 pwm mode 2 phase counting mode 1 phase counting mode 2 phase counting mode 3 phase counting mode 4 mode 1 1 * 0 1 0 1 * 0 1 0 1 0 1 0 1 * * : don t care notes: 1. md3 is a reserved bit. in a write, it should always be written with 0. 2. phase counting mode cannot be set for channels 0 and 3. in this case, 0 should always be written to md2. 0 tgra operates normally tgra and tgrc used together for buffer operation tgra buffer operation 1 0 tgrb operates normally tgrb and tgrd used together for buffer operation tgrb buffer operation 1
613 tior0h?imer i/o control register 0h h'ffd2 tpu0 bit initial value read/write 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w 0 ioa0 0 r/w 0 0 tgr0a i/o control 0 0 1 tgr0a is output compare register 10 1 100 1 10 1 0 1 0 0 tgr0a is input capture register 1 1 * output disabled initial output is 1 output output disabled initial output is 0 output capture input source is tioca0 pin 0 output at compare match 1 output at compare match toggle output at compare match * : don t care 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges ** 1 capture input source is channel 1/count clock input capture at tcnt1 count-up/ count-down 0 0 tgr0b i/o control 0 0 1 tgr0b is output compare register 10 1 100 1 10 1 0 1 0 0 tgr0b is input capture register 1 1 * output disabled initial output is 1 output output disabled initial output is 0 output capture input source is tiocb0 pin 0 output at compare match 1 output at compare match toggle output at compare match * : don t care 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges ** 1 capture input source is channel 1/count clock input capture at tcnt1 count-up/ count-down * 1 note: 1. when bits tpsc2 to tpsc0 in tcr1 are set to b 000 and /1 is used as the tcnt1 count clock, this setting is invalid and input capture does not occur.
614 tior0l?imer i/o control register 0l h'ffd3 tpu0 bit initial value read/write 7 iod3 0 r/w 6 iod2 0 r/w 5 iod1 0 r/w 4 iod0 0 r/w 3 ioc3 0 r/w 2 ioc2 0 r/w 1 ioc1 0 r/w 0 ioc0 0 r/w 0 0 tgr0c i/o control 0 0 1 tgr0c is output compare register 10 1 100 1 10 1 0 1 0 0 tgr0c is input capture register 1 1 * output disabled initial output is 1 output output disabled initial output is 0 output capture input source is tiocc0 pin 0 output at compare match 1 output at compare match toggle output at compare match * : don t care 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges ** 1 capture input source is channel 1/count clock input capture at tcnt1 count-up/ count-down 0 0 tgr0d i/o control 0 0 1 tgr0d is output compare register * 2 10 1 100 1 10 1 0 1 0 0 tgr0d is input capture register * 2 1 1 * output disabled initial output is 1 output output disabled initial output is 0 output capture input source is tiocd0 pin 0 output at compare match 1 output at compare match toggle output at compare match * : don t care 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges ** 1 capture input source is channel 1/count clock input capture at tcnt1 count-up/ count-down * 1 note: when the bfa bit in tmdr0 is set to 1 and tgr0c is used as a buffer register, this setting is invalid and input capture/output compare does not occur. notes: 1. when bits tpsc2 to tpsc0 in tcr1 are set to b 000 and /1 is used as the tcnt1 count clock, this setting is invalid and input capture does not occur. 2. when the bfb bit in tmdr0 is set to 1 and tgr0d is used as a buffer register, this setting is invalid and input capture does not occur. note: when tgrc or tgrd is designated for buffer operation, these settings are invalid and the register operates as a buffer register.
615 tier0?imer interrupt enable register 0 h'ffd4 tpu0 bit initial value read/write 7 ttge 0 r/w 6 1 5 0 4 tciev 0 r/w 3 tgied 0 r/w 2 tgiec 0 r/w 1 tgieb 0 r/w 0 tgiea 0 r/w 0 tgr interrupt enable a 1 0 tgr interrupt enable b 1 0 tgr interrupt enable c 1 0 tgr interrupt enable d 1 0 interrupt request (tciv) by tcfv disabled interrupt request (tciv) by tcfv enabled overflow interrupt enable 1 0 a/d conversion start request generation disabled a/d conversion start request generation enabled a/d conversion start request enable 1 interrupt request (tgia) by tgfa bit disabled interrupt request (tgia) by tgfa bit enabled interrupt request (tgib) by tgfb bit disabled interrupt request (tgib) by tgfb bit enabled interrupt request (tgic) by tgfc bit disabled interrupt request (tgic) by tgfc bit enabled interrupt request (tgid) by tgfd bit disabled interrupt request (tgid) by tgfd bit enabled
616 tsr0?imer status register 0 h'ffd5 tpu0 bit initial value read/write 7 1 6 1 5 0 4 tcfv 0 r/(w) * 3 tgfd 0 r/(w) * 2 tgfc 0 r/(w) * 1 tgfb 0 r/(w) * 0 tgfa 0 r/(w) * 0 tgra input capture/output compare flag 1 0 tgrb input capture/output compare flag 1 0 tgrc input capture/output compare flag 1 note: * can only be written with 0, to clear the flag. 0 tgrd input capture/output compare flag 1 0 [clearing condition] when 0 is written to tcfv after reading tcfv = 1 [setting condition] when the tcnt value overflows (from h'ffff to h'0000) overflow flag 1 [clearing conditions] when dtc is activated by tgia interrupt and disel bit in dtc s mrb register is 0 when dmac is activated by tgia interrupt and dta bit in dmac s dmabcr register is 1 when 0 is written to tgfa after reading tgfa = 1 [clearing conditions] when dtc is activated by tgib interrupt and disel bit in dtc s mrb register is 0 when 0 is written to tgfb after reading tgfb = 1 [setting conditions] when tcnt = tgrb while tgrb is functioning as output compare register when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register [clearing conditions] when dtc is activated by tgic interrupt and disel bit in dtc s mrb register is 0 when 0 is written to tgfc after reading tgfc = 1 [setting conditions] when tcnt = tgrc while tgrc is functioning as output compare register when tcnt value is transferred to tgrc by input capture signal while tgrc is functioning as input capture register [clearing conditions] when dtc is activated by tgid interrupt and disel bit in dtc s mrb register is 0 when 0 is written to tgfd after reading tgfd = 1 [setting conditions] when tcnt = tgrd while tgrd is functioning as output compare register when tcnt value is transferred to tgrd by input capture signal while tgrd is functioning as input capture register [setting conditions] when tcnt = tgra while tgra is functioning as output compare register when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register
617 tcnt0?imer counter 0 h'ffd6 tpu0 bit initial value read/write 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 10 0 r/w 9 0 r/w 8 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w up-counter tgr0a?imer general register 0a h'ffd8 tpu0 tgr0b?imer general register 0b h'ffda tpu0 tgr0c?imer general register 0c h'ffdc tpu0 tgr0d?imer general register 0d h'ffde tpu0 bit initial value read/write 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w
618 tcr1?imer control register 1 h'ffe0 tpu1 bit initial value read/write 7 0 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w 0 tpsc0 0 r/w 0 1 0 1 0 1 internal clock: count on /1 internal clock: count on /4 internal clock: count on /16 internal clock: count on /64 external clock: count on tclka pin input external clock: count on tclkb pin input internal clock: count on /256 count on tcnt2 overflow/underflow time prescaler 0 1 0 1 0 1 0 1 0 1 0 1 * count at rising edge count at falling edge count at both edges clock edge 0 tcnt clearing disabled tcnt cleared by tgra compare match/input capture tcnt cleared by tgrb compare match/input capture counter clear 0 1 10 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * note: this setting is invalid when channel 1 is in phase counting mode. note: * this setting is invalid when channel 1 is in phase counting mode. note: * synchronous operation is selected by setting the sync bit in tsyr to 1.
619 tmdr1?imer mode register 1 h'ffe1 tpu1 bit initial value read/write 7 1 6 1 5 0 4 0 3 md3 0 r/w 2 md2 0 r/w 1 md1 0 r/w 0 md0 0 r/w 0 0 normal operation reserved pwm mode 1 pwm mode 2 phase counting mode 1 phase counting mode 2 phase counting mode 3 phase counting mode 4 mode 1 1 * 0 1 0 1 * 0 1 0 1 0 1 0 1 * * : don t care note: md3 is a reserved bit. in a write, it should always be written with 0.
620 tior1?imer i/o control register 1 h'ffe2 tpu1 bit initial value read/write 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w 0 ioa0 0 r/w 0 0 tgr1a i/o control 0 0 1 tgr1a is output compare register 10 1 100 1 10 1 0 1 0 0 tgr1a is input capture register 1 1 * output disabled initial output is 1 output output disabled initial output is 0 output capture input source is tioca4 pin 0 output at compare match 1 output at compare match toggle output at compare match * : don t care 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges ** 1 capture input source is tgr0a compare match/ input capture input capture at generation of channel 0/tgr0a compare match/ input capture 0 0 tgr1b i/o control 0 0 1 tgr1b is output compare register 10 1 100 1 10 1 0 1 0 0 tgr1b is input capture register 1 1 * output disabled initial output is 1 output output disabled initial output is 0 output capture input source is tiocb1 pin 0 output at compare match 1 output at compare match toggle output at compare match * : don t care 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges ** 1 capture input source is tgr0c compare match/ input capture input capture at generation of tgr0c compare match/ input capture
621 tier1?imer interrupt enable register 1 h'ffe4 tpu1 bit initial value read/write 7 ttge 0 r/w 6 1 5 tcieu 0 r/w 4 tciev 0 r/w 3 0 2 0 1 tgieb 0 r/w 0 tgiea 0 r/w 0 tgr interrupt enable a 1 0 tgr interrupt enable b 1 0 interrupt request (tciv) by tcfv disabled interrupt request (tciv) by tcfv enabled overflow interrupt enable 1 0 a/d conversion start request generation disabled a/d conversion start request generation enabled a/d conversion start request enable 1 0 interrupt request (tciu) by tcfu disabled interrupt request (tciu) by tcfu enabled underflow interrupt enable 1 interrupt request (tgia) by tgfa bit disabled interrupt request (tgia) by tgfa bit enabled interrupt request (tgib) by tgfb bit disabled interrupt request (tgib) by tgfb bit enabled
622 tsr1?imer status register 1 h'ffe5 tpu1 bit initial value read/write 7 tcfd 1 r 6 1 5 tcfu 0 r/(w) * 4 tcfv 0 r/(w) * 3 0 2 0 1 tgfb 0 r/(w) * 0 tgfa 0 r/(w) * 0 tgra input capture/output compare flag 1 0 tgrb input capture/output compare flag 1 0 [clearing condition] when 0 is written to tcfv after reading tcfv = 1 [setting condition] when the tcnt value overflows (from h'ffff to h'0000) overflow flag 1 0 [clearing condition] when 0 is written to tcfu after reading tcfu = 1 [setting condition] when the tcnt value underflows (from h'0000 to h'ffff) underflow flag 1 0 tcnt counts down tcnt counts up count direction flag 1 note: * can only be written with 0, to clear the flag. [clearing conditions] when dtc is activated by tgia interrupt and disel bit in dtc s mrb register is 0 when dmac is activated by tgia interrupt and dta bit in dmac s dmabcr register is 1 when 0 is written to tgfa after reading [clearing conditions] when dtc is activated by tgib interrupt and disel bit in dtc s mrb register is 0 when 0 is written to tgfb after reading tgfb = 1 [setting conditions] when tcnt = tgra while tgra is functioning as output compare register when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register [setting conditions] when tcnt = tgrb while tgrb is functioning as output compare register when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register
623 tcnt1?imer counter 1 h'ffe6 tpu1 bit initial value read/write 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 10 0 r/w 9 0 r/w 8 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w up/down-counter * note: * this timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. in other cases it functions as an up-counter. tgr1a?imer general register 1a h'ffe8 tpu1 tgr1b?imer general register 1b h'ffea tpu1 bit initial value read/write 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w
624 tcr2?imer control register 2 h'fff0 tpu2 bit initial value read/write 7 0 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w 0 tpsc0 0 r/w 0 1 0 1 0 1 internal clock: count on /1 internal clock: count on /4 internal clock: count on /16 internal clock: count on /64 external clock: count on tclka pin input external clock: count on tclkb pin input external clock: count on tclkc pin input internal clock: count on /1024 time prescaler 0 1 0 1 0 1 0 1 0 1 0 1 * count at rising edge count at falling edge count at both edges clock edge 0 tcnt clearing disabled tcnt cleared by tgra compare match/input capture tcnt cleared by tgrb compare match/input capture counter clear 0 1 10 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * note: this setting is invalid when channel 2 is in phase counting mode. note: * this setting is invalid when channel 2 is in phase counting mode. note: * synchronous operation is selected by setting the sync bit in tsyr to 1.
625 tmdr2?imer mode register 2 h'fff1 tpu2 bit initial value read/write 7 1 6 1 5 0 4 0 3 md3 0 r/w 2 md2 0 r/w 1 md1 0 r/w 0 md0 0 r/w 0 0 normal operation reserved pwm mode 1 pwm mode 2 phase counting mode 1 phase counting mode 2 phase counting mode 3 phase counting mode 4 mode 1 1 * 0 1 0 1 * 0 1 0 1 0 1 0 1 * * : don t care note: md3 is a reserved bit. in a write, it should always be written with 0.
626 tior2?imer i/o control register 2 h'fff2 tpu2 bit initial value read/write 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w 0 ioa0 0 r/w 0 0 tgr2a i/o control 0 0 1 tgr2a is output compare register 10 1 100 1 10 1 * 1 0 0 tgr2a is input capture register 1 1 * output disabled initial output is 1 output output disabled initial output is 0 output capture input source is tioca2 pin 0 output at compare match 1 output at compare match toggle output at compare match * : don t care 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges 0 0 tgr2b i/o control 0 0 1 tgr2b is output compare register 10 1 100 1 10 1 * 1 0 0 tgr2b is input capture register 1 1 * output disabled initial output is 1 output output disabled initial output is 0 output capture input source is tiocb2 pin 0 output at compare match 1 output at compare match toggle output at compare match * : don t care 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges
627 tier2?imer interrupt enable register 2 h'fff4 tpu2 bit initial value read/write 7 ttge 0 r/w 6 1 5 tcieu 0 r/w 4 tciev 0 r/w 3 0 2 0 1 tgieb 0 r/w 0 tgiea 0 r/w 0 tgr interrupt enable a 1 0 tgr interrupt enable b 1 0 interrupt request (tciv) by tcfv disabled interrupt request (tciv) by tcfv enabled overflow interrupt enable 1 0 a/d conversion start request generation disabled a/d conversion start request generation enabled a/d conversion start request enable 1 0 interrupt request (tciu) by tcfu disabled interrupt request (tciu) by tcfu enabled underflow interrupt enable 1 interrupt request (tgia) by tgfa bit disabled interrupt request (tgia) by tgfa bit enabled interrupt request (tgib) by tgfb bit disabled interrupt request (tgib) by tgfb bit enabled
628 tsr2?imer status register 2 h'fff5 tpu2 bit initial value read/write 7 tcfd 1 r 6 1 5 tcfu 0 r/(w) * 4 tcfv 0 r/(w) * 3 0 2 0 1 tgfb 0 r/(w) * 0 tgfa 0 r/(w) * 0 tgra input capture/output compare flag 1 0 tgrb input capture/output compare flag 1 0 [clearing condition] when 0 is written to tcfv after reading tcfv = 1 [setting condition] when the tcnt value overflows (from h'ffff to h'0000) overflow flag 1 0 [clearing condition] when 0 is written to tcfu after reading tcfu = 1 [setting condition] when the tcnt value underflows (from h'0000 to h'ffff) underflow flag 1 0 tcnt counts down tcnt counts up count direction flag 1 note: * can only be written with 0, to clear the flag. [clearing conditions] when dtc is activated by tgia interrupt and disel bit in dtc s mrb register is 0 when dmac is activated by tgia interrupt and dta bit in dmac s dmabcr register is 1 when 0 is written to tgfa after reading [clearing conditions] when dtc is activated by tgib interrupt and disel bit in dtc s mrb register is 0 when 0 is written to tgfb after reading tgfb = 1 [setting conditions] when tcnt = tgra while tgra is functioning as output compare register when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register [setting conditions] when tcnt = tgrb while tgrb is functioning as output compare register when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register
629 tcnt2?imer counter 2 h'fff6 tpu2 bit initial value read/write 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 10 0 r/w 9 0 r/w 8 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w up/down-counter * note: * this timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. in other cases it functions as an up-counter. tgr2a?imer general register 2a h'fff8 tpu2 tgr2b?imer general register 2b h'fffa tpu2 bit initial value read/write 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w
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